Write once read only memory employing charge trapping in insulators
AssigneeMicron Technology, Inc.
InventorLeonard Forbes
Life of this patent
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Abstract
Structures and methods for write once read only memory employing charge trapping in insulators are provided. The write once read only memory cell includes a metal oxide semiconductor field effect transistor having a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, and a gate separated from the channel region by a gate insulator. A plug couples the first source/drain region to an array plate. A bitline is coupled to the second source/drain region. The MOSFET can be programmed by operation in a reverse direction trapping charge in the gate insulator adjacent to the first source/drain region such that the programmed MOSFET operates at reduced drain source current when read in a forward direction.
Claims17
A method for forming a memory cell, comprising:
- forming a transistor, including:
- forming a first source/drain region, a second source/drain region, and a channel region between the first and the second source/drain regions in a substrate;
- forming a single gate insulator in direct contact with the channel region;
- forming a gate above the single gate insulator in direct contact with the single gate insulator;
- and
- forming a circuit connected to the memory cell to program the memory cell in a reverse direction with a trapped charge in the gate insulator adjacent to the first source/drain region;
- wherein the single gate insulator has a thickness greater than or equal to 10 nanometers.
A method for forming a memory cell, comprising;
- forming a transistor, including:
- forming a first source/drain region, a second source/drain region, and a channel region between the first and the second source/drain regions in a substrate;
- forming a single silicon rich oxide gate insulator in direct contact with the channel region;
- forming a gate above the single silicon rich oxide gate insulator in direct contact with the single silicon rich oxide gate insulator;
- and
- forming a circuit connected to the memory cell to program the memory cell in a reverse direction with a trapped charge in the silicon rich oxide gate insulator adjacent to the first source/drain region;
- wherein the single silicon rich oxide gate insulator has a thickness greater than or equal to 10 nanometers.
A method for forming a memory cell, comprising:
- forming a transistor, including:
- forming a first source/drain region, a second source/drain region, and a channel region between the first and the second source/drain regions in a substrate;
- wet oxidizing a single silicon dioxide gate insulator in direct contact with the channel region;
- forming a gate above the single silicon dioxide gate insulator in direct contact with the silicon dioxide gate insulator;
- and
- forming a circuit connected to the memory cell to program the memory cell in a reverse direction with a trapped charge in the silicon dioxide gate insulator adjacent to the first source/drain region;
- wherein the single silicon dioxide gate insulator has a thickness greater than or equal to 10 nanometers.
A method for forming a memory cell, comprising:
- forming a transistor, including:
- forming a first source/drain region, a second source/drain region, and a channel region between the first and the second source/drain regions in a substrate;
- forming a single silicon oxynitride gate insulator in direct contact with the channel region;
- forming a gate above the single silicon oxynitride gate insulator in direct contact with the single silicon oxynitride gate insulator;
- and
- forming a circuit connected to the memory cell to program the memory cell in a reverse direction with a trapped charge in the silicon oxynitride gate insulator adjacent to the first source/drain region;
- wherein the single silicon oxynitride gate insulator has a thickness greater than or equal to 10 nanometers.
A method for forming a memory cell, comprising:
- forming a transistor, including:
- forming a first source/drain region, a second source/drain region, and a channel region between the first and the second source/drain regions in a substrate;
- forming a single aluminum oxide gate insulator in direct contact with the channel region;
- forming a gate above the aluminum oxide gate insulator in direct contact with the single alumlimim oxide gate insulator;
- and
- forming a circuit connected to the memory cell to program the memory cell in a reverse direction with a trapped charge in the aluminum oxide gate insulator adjacent to the first source/drain region;
- wherein the single aluminum oxide gate insulator has a thickness greater than or equal to 10 nanometers.
Dependencies are inferred from the claim text.