US 7,622,351 B2Granted

Method of manufacturing semiconductor device and semiconductor device

AssigneeNEC Electronics Corporation

InventorKenya Kobayashi

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Abstract

A method of manufacturing a semiconductor device, includes: forming a first and a second trench regions adjacent from each other in a first conductivity type semiconductor base; forming a second conductivity type semiconductor region in the semiconductor base between the first and second trench regions; forming a mask on the second conductivity type semiconductor region, the mask covering a central portion between the first and second trench regions; performing ion implantation of a first conductivity type impurity in the second conductivity type semiconductor region with the mask to form a first conductivity type first region and a first conductivity type second region separated from the first conductivity type first region; and performing heat treatment to diffuse the impurity in the first and second regions and to form a connection region between the first and second regions, connection region being shallower than the first and second regions after the heat treatment.

Claims11

Dependent claims

A method of manufacturing a semiconductor device, comprising:

forming a first trench region and a second trench region adjacent from each other in a first conductivity type semiconductor base;
forming a second conductivity type semiconductor region in said semiconductor base between said first trench region and said second trench region;
forming a mask on said second conductivity type semiconductor region, said mask covering a central portion between said first trench region and said second trench region;
performing ion implantation of a first conductivity type impurity in said second conductivity type semiconductor region with said mask to form a first conductivity type first region and a first conductivity type second region separated from said first conductivity type first region;
and
performing heat treatment to diffuse said impurity in said first conductivity type first region and said first conductivity type second region and to form a connection region between said first conductivity type first region and said first conductivity type second region, connection region being shallower than said first conductivity type first region and said first conductivity type second region after said heat treatment.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/348,467Filed 5 Jan 2009
Priority: JP 2008-00656316 Jan 2008
Published: US 2009/0179260 A116 Jul 2009
Granted: 24 Nov 2009
Term ends: Not estimatedThe source records don’t support an estimate.

Classification9 codes

H10D 30/668
Vertical dmos [vdmos] fets: having trench gate electrodes, e.g. UMOS transistors
H10D 30/0297
Of vertical dmos [vdmos] fets: using recessing of the gate electrodes, e.g. to form trench gate electrodes
H10D 62/127
Top-view geometrical layouts of the regions or the junctions: of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
H10D 62/155
Source regions of DMOS transistors: shapes