Method of manufacturing semiconductor device having cell transistor with recess channel structure

A method of manufacturing a semiconductor device comprising the steps of:

• (1) forming device separation portions at predetermined positions of a semiconductor silicon substrate and forming a first region, a second region and a third region defined by the device separation portions;
• (2) forming a recess at the first region of the semiconductor silicon substrate defined by the device separation portions;
• (3) forming an N-type well at the third region of the semiconductor silicon substrate defined by the device separation portions;
• (4) forming a gate insulating film on an upper surface of the semiconductor silicon substrate, an inner surface of the recess and upper surfaces of the device separation portions;
• (5) forming on the gate insulating film a polysilicon layer having an impurity concentration of less than 1.0×1020/cm3;
• (6) forming an N-type polysilicon layer by implanting N-type impurity ions into the polysilicon layer of which the impurity concentration is less than 1.0×1020/cm3 at the first region and the second region by at least one of a vapor diffusion method and a solid-phase diffusion method;
• (7) forming a P-type polysilicon layer by implanting P-type impurity ions into the polysilicon layer of which the impurity concentration is less than 1.0×1020/cm3 at the third region;
• (8) after the steps (6) and (7), forming at least one of metal silicide film and a metal film on the N-type polysilicon layer and the P-type polysilicon layer;
• (9) performing etching to form a gate electrode including the N-type polysilicon layer at each of the first region and second region and a gate electrode including the P-type polysilicon layer at the third region;
• (10) implanting N-type impurity ions into a surface of the semiconductor silicon substrate at both sides of the gate electrode formed at each of the first region and second region to form a cell transistor having a recess channel structure at the first region and an nMOSFET structure at the second region;
• and
• (11) implanting P-type impurity ions into a surface of the semiconductor silicon substrate at both sides of the gate electrode formed at the third region to form a pMOSFET structure at the third region.