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US 7,622,343 B2Granted
Laser processing method, method for forming a flash memory, insulated gate semiconductor device and method for forming the same
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorsShunpei Yamazaki, Yasuhiko Takemura
Life of this patent
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Abstract
A laser doping process comprising: irradiating a laser beam operated in a pulsed mode to a single crystal semiconductor substrate of a first conductive type in an atmosphere of an impurity gas which imparts the semiconductor substrate a conductive type opposite to said first conductive type and incorporating the impurity contained in said impurity gas into the surface of said semiconductor substrate, thereby modifying the type and/or the intensity of the conductive type thereof. Provides devices having a channel length of 0.5 μm or less and impurity regions 0.1 μm or less in depth.
Claims26
A method of manufacturing a semiconductor memory device comprising:
- forming a gate dielectric on a semiconductor substrate;
- forming a floating gate and a control gate over the gate dielectric wherein the control gate is located over and insulated from the floating gate;
- oxidizing at least side surfaces of the floating gate and the control gate to form an oxide layer;
- forming a first impurity region in the semiconductor substrate to a first depth not larger than 0.1 μm using at least the floating gate, the control gate and the oxide layer as a mask wherein;
- and
- forming a second impurity region in the semiconductor substrate to a second depth larger than the first death wherein a channel forming region is formed in the semiconductor substrate below the floating gate between the first impurity region and the second impurity region,
- wherein a channel length of the channel forming region is not larger than 0.3 μm, and
- wherein said first impurity region is not overlapped with said control gate.
5 more elements
A method of manufacturing a semiconductor memory device comprising:
- forming a gate dielectric on a semiconductor substrate;
- forming a floating gate and a control gate over the gate dielectric wherein the control gate is located over and insulated from the floating gate;
- oxidizing at least side surfaces of the floating gate and the control gate to form an oxide layer;
- forming a first impurity region in the semiconductor substrate to a first depth not larger than 0.1 μm using at least the floating gate, the control gate and the oxide layer as a mask;
- and
- forming a second impurity region in the semiconductor substrate to a second depth larger than the first death wherein a channel forming region is formed in the semiconductor substrate below the floating gate between the first impurity region and the second impurity region,
- wherein a channel length of the channel forming region is not larger than 0.5 μm, and
- wherein said first impurity region is offset from said control gate.
5 more elements
A method of manufacturing a semiconductor memory device comprising:
- forming a gate dielectric on a semiconductor substrate;
- forming a floating gate and a control gate over the gate dielectric wherein the control gate is located over and insulated from the floating gate;
- oxidizing at least side surfaces of the floating gate and the control gate to form an oxide layer;
- forming a first impurity region in the semiconductor substrate to a first depth not larger than 0.1 μm using at least the floating gate, the control gate and the oxide layer as a mask;
- and
- forming a second impurity region in the semiconductor substrate to a second depth larger than the first death wherein a channel forming region is formed in the semiconductor substrate below the floating gate between the first impurity region and the second impurity region,
- wherein a channel length of the channel forming region is not larger than 0.5 μm, and
- wherein said first impurity region is overlapped with said oxide layer to a length of not larger than 50 nm.
5 more elements
A method of manufacturing a semiconductor memory device comprising:
- forming a gate dielectric on a semiconductor substrate;
- forming a floating gate and a control gate over the gate dielectric wherein the control gate is located over and insulated from the floating gate;
- oxidizing at least side surfaces of the floating gate and the control gate to form an oxide layer;
- forming a first impurity region in the semiconductor substrate to a first depth not larger than 0.1 μm using at least the floating gate, the control gate and the oxide layer as a mask;
- and
- forming a second impurity region in the semiconductor substrate to a second depth larger than the first death wherein a channel forming region is formed in the semiconductor substrate below the floating gate between the first impurity region and the second impurity region,
- wherein a channel length of the channel forming region is not larger than 0.3 μm, and
- wherein said first impurity region is not overlapped with said floating gate.
5 more elements
A method of manufacturing a semiconductor memory device comprising:
- forming a gate dielectric on a semiconductor substrate;
- forming a floating gate and a control gate over the gate dielectric wherein the control gate is located over and insulated from the floating gate;
- oxidizing at least side surfaces of the floating gate and the control gate to form an oxide layer;
- forming a first impurity region in the semiconductor substrate to a first depth not larger than 0.1 μm using at least the floating gate, the control gate and the oxide layer as a mask;
- and
- forming a second impurity region in the semiconductor substrate to a second depth larger than the first death wherein a channel forming region is formed in the semiconductor substrate below the floating gate between the first impurity region and the second impurity region,
- wherein a channel length of the channel forming region is not larger than 0.3 μm, and
- wherein said first impurity region is offset from said control gate.
5 more elements
Dependencies are inferred from the claim text.