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US 7,622,326 B2Granted
Manufacturing process of a chip package structure
AssigneeVIA Technologies, Inc.
InventorsKwun-Yao Ho, Moriss Kung
Life of this patent
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AssigneeVIA Technologies, Inc.
InventorsKwun-Yao Ho, Moriss Kung
Estimating the term…
A manufacturing process of a chip package structure is provided. The manufacturing method uses fine pitch circuit processes, such as a TFT-LCD process or an IC process, to increase layout density and shorten electrical transmission pathways so that a higher electrical performance level is attained. First, a multi-layered interconnection structure with high-density bonding pads and fine pitch circuit is formed over a hard support base plate having a large area and high degree of planarity. A die is attached to a top surface of the multi-layered interconnection structure. A plurality of opening is formed on a bottom surface of the support base plate. Contacts are positioned into the openings in the support base plate such that the contacts are electrically connected to an inner circuit within the multi-layered interconnection structure.
A method of fabricating a chip package, at least comprising the steps of:
Dependencies are inferred from the claim text.
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From the US filing history. Foreign family members aren’t listed.
Manufacture or treatment: of insulating or insulated package substrates, or of interposers, or of redistribution layers
For supporting or gripping: using temporarily an auxiliary support
Shapes or dispositions thereof: comprising multiple insulating layers
Package configurations: characterised by multiple insulating or insulated package substrates, interposers or RDLs
Term ended 21 Oct 2024 (estimated)
1. Field of Invention
The present invention relates to a chip package structure and manufacturing process thereof. More particularly, the present invention relates to a chip package structure with an insulating material fabricated hard support plate therein and manufacturing process thereof.
2. Description of Related Art
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings,
FIG. 1 is a schematic cross-sectional view showing the structure of a conventional flip chip ball grid array package; and
FIGS. 2A to 2G are schematic cross-sectional views showing the steps for fabricating a chip package structure according to one preferred embodiment of this invention.
Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
FIGS. 2A to 2G are schematic cross-sectional views showing the steps for fabricating a chip package structure according to one preferred embodiment of this invention. First, as shown in FIG. 2A, a support base plate 202 is provided. The support base plate 202 is fabricated using an insulating material including, for example, glass, quartz or ceramics. In addition, the support base plate must have a high degree of surface planarity.
As shown in FIG. 2B, an isolating base layer 204 is formed over the support base plate 202. The isolating base layer 204 can be planarized optionally so that the surface of the isolating base layer 204 can have a high degree of planarity as well. The isolating base layer 204 is fabricated using a material including, for example, polymer, polyester, polyimide, epoxy resin, acrylic and benzocyclobutene (BCB). Furthermore, the isolating base layer 204 can be attached to the surface of the support base plate 202 by performing either a film attachment process or a film coating process.