CMOS image sensor and manufacturing method thereof
AssigneeSamsung Electronics Co., Ltd.
InventorByung-jun Park
Life of this patent
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Abstract
A CMOS image sensor includes isolation regions and a photo diode region formed in a substrate, gate electrodes formed on the substrate, impurity injection regions formed in the substrate respectively positioned between the gate electrodes and the isolation regions, silicide regions formed on upper surfaces of the gate electrodes and the impurity injection regions, a first insulating layer formed on a surface of the photodiode region and sides of the gate electrodes, a second insulating layer formed on the first insulating layer, a third insulating layer formed on the second insulating layer, an interlayer insulating layer formed to cover the third insulating layer, and via plugs vertically passing through the interlayer insulating layer and connected to the silicide regions.
Claims12
A method of manufacturing a CMOS image sensor, the method comprising:
- forming isolation regions in a substrate;
- forming a first insulating layer on an entire surface of the substrate;
- forming gate electrodes on the first insulating layer;
- forming a photodiode region in the substrate;
- forming first impurity injection regions, each serving as one of a source and a drain of the gate electrodes;
- forming a second insulating layer covering the first insulating layer and the gate electrodes;
- forming patterns of the second insulating layer exposing the first insulating layer formed on the first impurity injection regions and forming first spacers on sides of the gate electrodes;
- forming second impurity injection regions, each serving as one of a source and a drain of the gate electrodes;
- removing the patterns of the second insulating layer;
- forming a third insulating layer covering a result of removing the patterns of the second insulating layer;
- forming a fourth insulating layer to cover the third insulating layer;
- forming a fifth insulating layer to cover the fourth insulating layer;
- etching the fourth and fifth insulating layers exposing the third insulating layer formed on upper portions of the gate electrodes and on surfaces of the second impurity injection regions, and forming patterns of the fourth and fifth insulating layer forming second spacers on the sides of the gate electrodes;
- removing the fifth insulating layer pattern;
- removing an exposed third insulating layer exposing the first insulating layer formed on the upper portions of the gate electrodes and the surfaces of the second impurity injection regions;
- removing an exposed first insulating layer exposing the upper surfaces of the gate electrodes and the surfaces of the second impurity injection regions;
- forming metal layers on the upper surfaces of the gate electrodes and the surfaces of the second impurity injection regions;
- forming silicide layers by heating the metal layers;
- forming a sixth insulating layer covering a result of forming the silicide layers;
- forming an interlayer insulating layer covering the sixth insulating layer;
- and
- forming via plugs vertically passing through the interlayer insulating layer and connected to the silicide layers.
Dependencies are inferred from the claim text.