Fabrication of three dimensional integrated circuit employing multiple die panels
AssigneeFreescale Semiconductor, Inc.
InventorsRobert E. Jones, Scott K. Pozder
Life of this patent
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AssigneeFreescale Semiconductor, Inc.
InventorsRobert E. Jones, Scott K. Pozder
Estimating the term…
A method of assembling an electronic device includes testing a first wafer of first die to identify the location of functional first die and dividing the first wafer into a set of panels, wherein a panel includes an M×N array of first die. A panel is bonded to a panel site of a second wafer to form a panel stack wherein a panel site defines an M×N array of second die in the second wafer. The panel stack is sawed into a devices comprising a first die bonded to a second die. Dividing the first wafer into panels may be done according statically or dynamically (to maximize the number of panels having a yield exceeding a specified threshold). Binning of the panels and panel sites according to functional die patterns may be performed to preferentially bond panels to panel sites of the same bin.
A method of assembling of an electronic device, comprising:
A method of assembling of an electronic device, comprising:
A method of assembling an electronic device, comprising:
Dependencies are inferred from the claim text.