Programmable delay circuit

A delay circuit for delaying an input signal, the delay circuit comprising:

• capacitance means having a threshold voltage, capacitance of the capacitance means being dependent, at least in part, on the threshold voltage, the capacitance means discharging at a discharge rate in response to an edge of the input signal;
• and
• means for triggering an output signal when the discharging capacitance means reaches a triggering voltage, the triggering voltage being dependent, at least in part, on the threshold voltage to determine a discharge time period,
• wherein the discharge time period determined from the dependence of the triggering voltage on the threshold voltage compensates for the discharge rate in the discharging of the capacitance means due to the dependence of the capacitance means on the threshold voltage.

A method for delaying an input signal comprising:

• discharging a capacitor at a discharge rate based on a capacitance dependent on a threshold voltage associated with the capacitor after an edge of the input signal is detected;
• and
• triggering an output when the discharging capacitor reaches a triggering voltage, the triggering voltage being at least partly dependent on the threshold voltage to determine a discharge time period,
• wherein the discharge time period determined from the dependence of the triggering voltage on the threshold voltage compensates for the discharge rate in the discharging of the capacitor due to the dependence of the capacitor on the threshold voltage.

A delay circuit for delaying an input signal, the delay circuit comprising:

• a rising edge delay cell comprising:
• a rising edge detector circuit, the rising edge detector circuit
• detecting a rising edge of the input signal;
• a rising edge capacitor, the rising edge capacitor in communication with the rising edge detector circuit and having a first transistor with a threshold voltage, a discharge rate and a capacitance of the rising edge capacitor being dependent, at least in part, on the threshold voltage;
• and
• a rising edge triggering circuit having a rising edge input and a rising edge output, the rising edge input in communication with the rising edge capacitor, the rising edge triggering circuit having a second transistor with the threshold voltage, and a rising edge triggering voltage to generate the rising edge output, the rising edge output being dependent, at least in part, on the threshold voltage to determine a discharge time period,
• wherein the discharge time period determined from the dependence of the rising edge triggering voltage on the threshold voltage compensates for the discharge rate in the discharging of the rising edge capacitor due to the dependence of the rising edge capacitor on the threshold voltage.

A delay circuit comprising:

• a capacitor;
• first triggering circuit in communication with the capacitor and operative to generate a first triggering output when the capacitor reaches a first triggering level;
• second triggering circuit in communication with the capacitor and operative to generate a second triggering output when the capacitor reaches a second triggering level, the first triggering level being greater than the second triggering level;
• and
• pull down circuit operative to pull down a voltage of the capacitor when the first triggering circuit generates the first triggering output.

A delay circuit comprising:

• capacitance means;
• first triggering means for triggering a first triggering output when a voltage of the capacitance means reaches a first triggering level;
• first triggering means for triggering a second triggering output when the voltage of the capacitance means reaches a second triggering level, the first triggering level being greater than the second triggering level;
• and
• means for pulling down the voltage of the capacitance means when the first triggering means generates the first triggering output.

A method for delaying an input signal comprising:

• discharging a capacitor at a first rate;
• generating a first triggering voltage when a voltage of the capacitor reaches a first triggering level;
• pulling down the voltage of the capacitor at a second rate when the first triggering voltage is generated, the second rate being greater than the first rate;
• and
• generating a second triggering voltage when the voltage of the capacitor reaches a second triggering level.