# US 7,614,033 B2 · Mask data preparation > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,614,033 B2 - Document ID: US7614033B2 - Status: Granted - Kind: B2 - Application number: 11/442,110 - Filed: 2006-05-26 - Published: 2006-09-28 - Granted: 2009-11-03 - Earliest claimed: 2006-05-26 - Assignees: Takumi Technology Corporation - Inventors: Christophe Pierrat; Alfred Kwok-Kit Wong - Web page: https://patentgrep.com/patent/US7614033B2 ## CPC - G03F 1/36: Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes - G03F 1/68: Preparation processes not covered by groups G03F1/20 - G03F1/50 - G03F: PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR; (phototypographic composing devices B41B; photosensitive materials or processes for photographic purposes G03C; electrophotography, sensitive layers or processes therefor G03G) ## Abstract The manufacturing of integrated circuits relies on the use of optical proximity correction (OPC) to correct the printing of the features on the wafer. The data is subsequently fractured to accommodate the format of existing mask writer. The complexity of the correction after OPC can create some issues for vector-scan e-beam mask writing tools as very small slivers are created when the data is converted to the mask write tool format. Moreover the number of shapes created after fracturing is quite large and are not related to some important characteristics of the layout like for example critical areas. A new technique is proposed where the order of the OPC and fracturing steps is reversed. The fracturing step is done first in order to guarantee that no slivers are created and that the number of shapes is minimized. The shapes created can also follow the edges of critical zones so that critical and non-critical edges can be differentiated during the subsequent OPC step. ## Claims ### Claim 1 A method for performing proximity effect correction on a layout of an integrated circuit defined by a computer readable layout file, to produce a corrected layout file, the method comprising: receiving a polygon from the computer readable layout file, the polygon corresponding to a portion of the integrated circuit and having a given size; performing using a data processor a fragmentation of the polygon into a set of smaller shapes, based upon parameters of a manufacturing tool used for producing the integrated circuit, wherein said manufacturing tool is distinct from said data processor, and wherein the parameters are associated to characteristics of the manufacturing tool and not associated to dimensions of the polygon; performing using a data processor a proximity effect correction of at least one of the smaller shapes in the set of smaller shapes to provide a computer readable corrected layout file comprising a modified set of smaller shapes; and providing the computer readable corrected layout file to said manufacturing tool. ### Claim 2 (depends on 1) The method of claim 1, wherein the manufacturing tool comprises a mask writer. ### Claim 3 (depends on 1) The method of claim 1, wherein the manufacturing tool comprises a vector scan, e-beam tool, and said parameters comprise scanning dimensions of said vector scan, e-beam tool. ### Claim 4 (depends on 1) The method of claim 1, wherein one of said parameters is a minimum dimension for the manufacturing tool, and the fragmentation is such that the smaller shapes do not have a dimension smaller than said minimum dimension after said proximity effect correction. ### Claim 5 (depends on 1) The method of claim 1, wherein one of said parameters is a maximum dimension for the manufacturing tool, and the fragmentation is such that the smaller shapes do not have a dimension larger than said maximum dimension after said proximity effect correction. ### Claim 6 (depends on 1) The method of claim 1, wherein the corrected layout file is used to make a binary mask. ### Claim 7 (depends on 1) The method of claim 1, wherein the corrected layout file is used to make an attenuated phase-shifting mask. ### Claim 8 (depends on 1) The method of claim 1, wherein the corrected layout file is used to make a tri-tone phase-shifting mask. ### Claim 9 (depends on 1) The method of claim 1, wherein the corrected layout file is used to make an alternating aperture phase-shifting mask. ### Claim 10 (depends on 9) The method of claim 9, wherein two edges of one of the shapes in the set of smaller shapes are adjacent to two distinct phase-shifting regions, the two phase-shifting regions are substantially out of phase, and including storing information indicating that said two edges of one of the shapes in the set of smaller shapes are adjacent to two distinct phase-shifting regions. ### Claim 11 (depends on 10) The method of claim 10, wherein said information about the two edges is used to facilitate the phase assignment of the phase-shifting regions. ### Claim 12 (depends on 1) The method of claim 1, wherein at least one edge of one shape abuts a boundary of a critical area of the layout. ### Claim 13 (depends on 1) The method of claim 1, wherein the manufacturing tool comprises a mask inspection tool. ### Claim 14 (depends on 1) The method of claim 1, wherein a second polygon within proximity range of the polygon is taken into account in the fragmentation of the shapes. ### Claim 15 (depends on 14) The method of claim 14, wherein a corner of the second polygon is used in the fragmentation of the shapes. ### Claim 16 A mask for defining a layer of material, said mask comprising: a mask substrate; a layout data file used to create a layout pattern on the mask substrate; said layout pattern comprising material or physical shapes for transfer of an image to a workpiece; and said layout pattern having at least one shape having at least one segment corrected for proximity effects, said such shape was defined before correction by fragmenting a polygon of the layout data file, based upon parameters of a manufacturing tool used for producing the mask, wherein the parameters are associated to characteristics of the manufacturing tool and not associated to dimensions of the polygon. ### Claim 17 A method for manufacturing integrated circuits, said integrated circuits being defined by a computer readable layout file, the method comprising: receiving a polygon from the computer readable layout file, the polygon corresponding to a portion of an integrated circuit and having a given size; performing using a data processor a fragmentation of the polygon into a set of smaller shapes, based upon parameters of a manufacturing tool used for producing the integrated circuit, wherein said manufacturing toll is distinct from said data processor, and wherein the parameters are associated to characteristics of the manufacturing tool and not associated to dimensions of the polygon; performing using a data processor a proximity effect correction of at least one of the smaller shapes in the set of smaller shapes to provide a computer readable corrected layout file comprising a modified set of smaller shapes; providing the computer readable corrected layout file to said manufacturing tool; producing a mask having a mask layout based on the corrected layout file; and exposing a semiconductor treated with a material sensitive to radiation energy to said radiation energy using said mask. ### Claim 18 (depends on 17) The method of claim 17, wherein the mask is produced using a vector scan, e-beam tool by exposing a mask blank coated with an e-beam sensitive resist and said resist polarity is chosen such that the shapes representing the critical dimensions of the layout are exposed on the mask. ### Claim 19 A method for producing a mask for a layer on an integrated circuit represented by a computer readable layout file, comprising: receiving a polygon from the computer readable layout file, the polygon corresponding to a portion of the integrated circuit and having a given size; performing using a data processor a fragmentation of the polygon into a set of smaller shapes, based upon parameters of a manufacturing tool used for producing the integrated circuit, wherein said manufacturing tool is distinct from said data processor, and wherein the parameters are associated to characteristics of the manufacturing tool and not associated to dimensions of the polygon; performing using a data processor a proximity effect correction of at least one of the smaller shapes in the set of smaller shapes to provide a computer readable corrected layout file comprising a modified set of smaller shapes; and producing a mask having a mask layout based on the corrected layout file. ### Claim 20 A system for producing layout data, comprising: a data processor which executes programs of instruction; memory accessible by the data processor and storing the programs of instruction, the programs of instruction including logic to receive a polygon of a computer readable layout file of a portion of an integrated circuit and having a given size, performing using a data processor a fragmentation of the polygon into a set of smaller shapes, based upon parameters of a manufacturing tool used for producing the integrated circuit, wherein said manufacturing tool is distinct from said data processor, and wherein the parameters are associated to characteristics of the manufacturing tool and not associated to dimensions of the polygon, and performing using a data processor a proximity effect correction of at least one of the smaller shapes in the set of smaller shapes to provide a computer readable corrected layout file comprising a modified set of smaller shapes. ### Claim 21 A program of instructions to be executed by a data processor, including logic to receive a polygon of a computer readable layout file of a portion of an integrated circuit and having a given size, logic to perform a fragmentation of the polygon into a set of smaller shapes, based upon parameters of a manufacturing tool used for producing the integrated circuit, wherein said manufacturing tool is distinct from said data processor, and wherein the parameters are associated to characteristics of the manufacturing tool and not associated to dimensions of the polygon, and logic to perform a proximity effect correction of at least one of the smaller shapes in the set of smaller shapes to provide a computer readable corrected layout file comprising a modified set of smaller shapes. ### Claim 22 A method for performing proximity effect correction on a layout of an integrated circuit defined by a computer readable layout file, to produce a corrected layout file, the method comprising: receiving a polygon from the computer readable layout file, the polygon corresponding to a portion of the integrated circuit and having a given size; performing using a data processor a fragmentation of at least one edge of the polygon into a set of segments, based upon parameters of a manufacturing tool used for producing the integrated circuit, wherein said manufacturing tool is distinct from said data processor, and wherein the parameters are associated to characteristics of the manufacturing tool and not associated to dimensions of the polygon; performing using a data processor a proximity effect correction of at least one of the segments in the set of segments to provide a computer readable corrected layout file; and providing the computer readable corrected layout file to said manufacturing tool. ### Claim 23 A method for manufacturing integrated circuits, said integrated circuits being defined by a layout file, the method comprising: receiving a polygon from the computer readable layout file, the polygon corresponding to a portion of an integrated circuit and having a given size; performing using a data processor a fragmentation of at least one edge of the polygon into a set of segments, based upon parameters of a manufacturing tool used for implementing the integrated circuit, wherein said manufacturing tool is distinct from said data processor, and wherein the parameters are associated to characteristics of the manufacturing tool and not associated to dimensions of the polygon; performing using a data processor a proximity effect correction of at least one of the segments in the set of segments to provide a computer readable corrected layout file; producing a mask having a mask layout based on the corrected layout file; and exposing a semiconductor treated with a material sensitive to radiation energy to said radiation energy using said mask. ### Claim 24 (depends on 23) The method of claim 23, where the mask is produced using a vector-scan e-beam tool by exposing a mask blank coated with an e-beam sensitive resist and said resist polarity is chosen such that the shapes representing the critical dimensions of the layout are exposed on the mask.