# US 7,614,032 B2 · Method for correcting a mask design layout

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- Number: US 7,614,032 B2
- Document ID: US7614032B2
- Status: Granted
- Kind: B2
- Application number: 11/637,209
- Filed: 2006-12-11
- Published: 2007-07-19
- Granted: 2009-11-03
- Earliest claimed: 2006-12-11
- Assignees: The Regents of the Univerisity of California; The Regents of the University of Michigan
- Inventors: Andrew B. Kahng; Puneet Gupta; Dennis Sylvester; Jie Yang
- Web page: https://patentgrep.com/patent/US7614032B2

## CPC

- G06F 30/39: Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A method for performing a mask design layout resolution enhancement includes determining a level of correction for the design layout for a predetermined parametric yield with a minimum total correction cost. The design layout is corrected at the determined level of correction based on a correction algorithm if the correction is required. In this manner, only those printed features on the design layout that are critical for obtaining the desired performance yield are corrected, thereby reducing the total cost of correction of the design layout.

## Claims

### Claim 1

A method for performing a mask design layout to be printed, the method comprising:
determining a first level of correction for a mask design layout by using a computer system for a predetermined parametric yield with a minimum total correction cost; and
correcting the mask design layout at said first level of correction based on a correction algorithm if said first level of correction is determined to be required.

### Claim 2 (depends on 1)

The method as defined in claim 1 further including determining a second level of correction for the mask design layout for said predetermined parametric yield after correcting the mask design layout at said first determined level of correction.

### Claim 3 (depends on 2)

The method as defined in claim 2 further including, correcting the mask design layout at said second level of correction based on said correction algorithm if said second level of correction is determined to be required.

### Claim 4 (depends on 3)

The method as defined in claim 3 wherein the mask design layout is not corrected if it is determined that said second level of correction is not required.

### Claim 5 (depends on 1)

The method as defined in claim 1, wherein determining the first level of correction includes identifying features from a yield library.

### Claim 6 (depends on 5)

The method as defined in claim 5, wherein determining the first level of correction includes using a synthesis tool to selectively choose features from the yield library to meet the predetermined parametric yield.

### Claim 7 (depends on 6)

The method as defined in claim 6, wherein selected features from the yield library are identical and have different areas and timing.

### Claim 8 (depends on 1)

The method as defined in claim 1, wherein determining the first level of correction includes identifying discrete levels of correction.

### Claim 9 (depends on 1)

The method as defined in claim 1, wherein determining the first level of correction includes using exact variation tolerances that are computed independently for layout features of the mask design layout.

### Claim 10 (depends on 1)

The method as defined in claim 1, wherein determining the first level of correction includes obtaining a probability density function.

### Claim 11 (depends on 1)

The method as recited in claim 1, wherein a statistical static timing analysis (SSTA) or static timing analysis (STA) is performed in determining the first level of correction.

### Claim 12 (depends on 1)

The method as recited in claim 1, further comprising: printing the mask design layout to define a mask after the first level of correction or after additional levels of correction.

### Claim 13 (depends on 12)

The method as recited in claim 12, wherein the mask is used to define features of a circuit during integrated circuit fabrication.