# US 7,614,028 B1 · Representation, configuration, and reconfiguration of routing method and system > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,614,028 B1 - Document ID: US7614028B1 - Status: Granted - Kind: B1 - Application number: 11/741,668 - Filed: 2007-04-27 - Granted: 2009-11-03 - Earliest claimed: 2006-04-28 - Assignees: Cadence Design Systems, Inc. - Inventors: Eric Nequist; Richard Brashears - Web page: https://patentgrep.com/patent/US7614028B1 ## CPC - G06F 30/394: Routing (G06F30/396 takes precedence) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Disclosed is an improved method, system, and article of manufacture for implementing routing for an electrical circuit and chip design. A routing architecture can be represented as a spectrum of different granular routing levels. Instead of routing based upon area, routing can be performed for specific routes or portions of routes. Different types of representation or levels of abstraction for the routing can be used for the same net or route. Partial topological reconfiguration, refinement, or rip-up can be performed for a portion of the integrated circuit design, where the portion is smaller than an entire route or net. Non-uniform levels of routing activities or resources may be applied to route the design. Prioritization may be used to route certain portions of the design with greater levels of detail, abstraction, or resources than other portions of the design. ## Claims ### Claim 1 A method implemented with a processor, comprising: identifying one or more routes for an integrated circuit design; representing a first portion of the one or more routes at a first level of abstraction, wherein the first level of abstraction corresponds to a route representation having semantics that allow interface with other levels of abstraction; representing a second portion of the one or more routes at a second level of abstraction, the second level of abstraction having a greater amount of routing detail as compared to the first level of abstraction, wherein the second level of abstraction corresponds to a route representation having semantics that allow interface with other levels of abstraction; and storing the one or more routes in a computer usable medium. ### Claim 2 (depends on 1) The method of claim 1 in which only a portion of a route is routed. ### Claim 3 (depends on 1) The method of claim 1 in which routing is performed using at least three routing abstraction levels. ### Claim 4 (depends on 1) The method of claim 1 which one of the abstraction levels from the first or second abstraction levels is either a guide representation, global segment representation, global via representation, detail segment representation, detail via representation, imaged geometry representation, or electrical characteristics representation. ### Claim 5 (depends on 1) The method of claim 1 in which routing is performed relative to imaged geometry. ### Claim 6 (depends on 1) The method of claim 1 in which routing is performed relative to electrical representation. ### Claim 7 (depends on 1) The method of claim 1 in which routing is performed relative to guides. ### Claim 8 (depends on 1) The method of claim 1 in which greater resources are applied to higher priority portions of the integrated circuit design. ### Claim 9 (depends on 1) The method of claim 1 in which lower priority portions of the integrated circuit design are routed at higher abstraction levels. ### Claim 10 (depends on 1) The method of claim 1 in which higher priority portions of the integrated circuit design are routed at lower abstraction levels. ### Claim 11 (depends on 1) The method of claim 1 in which non-uniform routing is performed. ### Claim 12 (depends on 1) The method of claim 1 in which rules are used to guide the routing. ### Claim 13 (depends on 12) The method of claim 12 in which the rules identify amount or proportion of system resources to apply to particular portions of the integrated circuit design. ### Claim 14 (depends on 12) The method of claim 12 in which the rules identify particular portions of the integrated circuit design that should be routed earlier or later in the process. ### Claim 15 (depends on 12) The method of claim 12 in which the rules identify layout parameters. ### Claim 16 (depends on 15) The method of claim 15 in which the layout parameters comprise width or spacing. ### Claim 17 (depends on 1) The method of claim 1 in which different abstraction levels of representation are used along the same route. ### Claim 18 (depends on 1) The method of claim 1 in which the integrated circuit design is routed with a non-uniform progression of routing. ### Claim 19 (depends on 1) The method of claim 1 in which parallel processing is applied to route different portions of the integrated circuit design. ### Claim 20 A system for routing an integrated circuit design, comprising: means for identifying one or more routes for an integrated circuit design; means for representing a first portion of the one or more routes at a first level of abstraction, wherein the first level of abstraction corresponds to a route representation having semantics that allow interface with other levels of abstraction; and means for representing a second portion of the one or more routes at a second level of abstraction, the second level of abstraction having a greater amount of routing detail as compared to the first level of abstraction, wherein the second level of abstraction corresponds to a route representation having semantics that allow interface with other levels of abstraction. ### Claim 21 (depends on 20) The system of claim 20 in which only a portion of a route is routed. ### Claim 22 (depends on 20) The system of claim 20 in which routing is performed using at least three routing abstraction levels. ### Claim 23 (depends on 20) The system of claim 20 which one of the abstraction levels from the first or second abstraction levels is either a guide representation, global segment representation, global via representation, detail segment representation, detail via representation, imaged geometry representation, or electrical characteristics representation. ### Claim 24 (depends on 20) The system of claim 20 in which routing is performed relative to imaged geometry. ### Claim 25 (depends on 20) The system of claim 20 in which routing is performed relative to electrical representation. ### Claim 26 (depends on 20) The system of claim 20 in which routing is performed relative to guides. ### Claim 27 (depends on 20) The system of claim 20 in which greater resources are applied to higher priority portions of the integrated circuit design. ### Claim 28 (depends on 20) The system of claim 20 in which lower priority portions of the integrated circuit design are routed at higher abstraction levels. ### Claim 29 (depends on 20) The system of claim 20 in which higher priority portions of the integrated circuit design are routed at lower abstraction levels. ### Claim 30 (depends on 20) The system of claim 20 in which non-uniform routing is performed. ### Claim 31 (depends on 20) The system of claim 20 in which rules are used to guide the routing. ### Claim 32 (depends on 31) The system of claim 31 in which the rules identify amount or proportion of system resources to apply to particular portions of the integrated circuit design. ### Claim 33 (depends on 31) The system of claim 31 in which the rules identify particular portions of the integrated circuit design that should be routed earlier or later in the process. ### Claim 34 (depends on 31) The system of claim 31 in which the rules identify layout parameters. ### Claim 35 (depends on 34) The system of claim 34 in which the layout parameters comprise width or spacing. ### Claim 36 (depends on 20) The system of claim 20 in which different abstraction levels of representation are used along the same route. ### Claim 37 (depends on 20) The system of claim 20 in which the integrated circuit design is routed with a non- uniform progression of routing. ### Claim 38 (depends on 20) The system of claim 20 in which parallel processing is applied to route different portions of the integrated circuit design. ### Claim 39 A computer program product that includes a computer readable medium, the computer readable medium comprising a plurality of computer instructions which, when executed by a processor, cause the processor to execute performing a process for routing an integrated circuit design, the process comprising: identifying one or more routes for an integrated circuit design; representing a first portion of the one or more routes at a first level of abstraction, wherein the first level of abstraction corresponds to a route representation having semantics that allow interface with other levels of abstraction; representing a second portion of the one or more routes at a second level of abstraction, the second level of abstraction having a greater amount of routing detail as compared to the first level of abstraction, wherein the second level of abstraction corresponds to a route representation having semantics that allow interface with other levels of abstraction; and storing the one or more routes in a computer usable medium. ### Claim 40 (depends on 39) The computer program product of claim 39 in which only a portion of a route is routed. ### Claim 41 (depends on 39) The computer program product of claim 39 in which routing is performed using at least three routing abstraction levels. ### Claim 42 (depends on 39) The computer program product of claim 39 which one of the abstraction levels from the first or second abstraction levels is either a guide representation, global segment representation, global via representation, detail segment representation, detail via representation, imaged geometry representation, or electrical characteristics representation. ### Claim 43 (depends on 39) The computer program product of claim 39 in which routing is performed relative to imaged geometry. ### Claim 44 (depends on 39) The computer program product of claim 39 in which routing is performed relative to electrical representation. ### Claim 45 (depends on 39) The computer program product of claim 39 in which routing is performed relative to guides. ### Claim 46 (depends on 39) The computer program product of claim 39 in which greater resources are applied to higher priority portions of the integrated circuit design. ### Claim 47 (depends on 39) The computer program product of claim 39 in which lower priority portions of the integrated circuit design are routed at higher abstraction levels. ### Claim 48 (depends on 39) The computer program product of claim 39 in which higher priority portions of the integrated circuit design are routed at lower abstraction levels. ### Claim 49 (depends on 39) The computer program product of claim 39 in which non-uniform routing is performed. ### Claim 50 (depends on 39) The computer program product of claim 39 in which rules are used to guide the routing. ### Claim 51 (depends on 50) The computer program product of claim 50 in which the rules identify amount or proportion of system resources to apply to particular portions of the integrated circuit design. ### Claim 52 (depends on 50) The computer program product of claim 50 in which the rules identify particular portions of the integrated circuit design that should be routed earlier or later in the process. ### Claim 53 (depends on 50) The computer program product of claim 50 in which the rules identify layout parameters. ### Claim 54 (depends on 53) The computer program product of claim 53 in which the layout parameters comprise width or spacing. ### Claim 55 (depends on 39) The computer program product of claim 39 in which different abstraction levels of representation are used along the same route. ### Claim 56 (depends on 39) The computer program product of claim 39 in which the integrated circuit design is routed with a non-uniform progression of routing. ### Claim 57 (depends on 39) The computer program product of claim 39 in which parallel processing is applied to route different portions of the integrated circuit design.