# US 7,614,020 B2 · Structurally field-configurable semiconductor array for in-memory processing of stateful, transaction-oriented systems

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- Number: US 7,614,020 B2
- Document ID: US7614020B2
- Status: Granted
- Kind: B2
- Application number: 11/426,880
- Filed: 2006-06-27
- Published: 2006-12-28
- Granted: 2009-11-03
- Earliest claimed: 2005-06-27
- Assignees: iKoa Corporation
- Inventors: Shridhar Mukund; Anjan Mitra
- Web page: https://patentgrep.com/patent/US7614020B2

## CPC

- G06F 15/7821: {Tightly coupled to memory, e.g. computational memory, smart memory, processor in memory}
- G06F 15/7867: {with reconfigurable architecture}
- G06F 30/30: Circuit design
- G06F 30/327: Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
- G06F 30/3323: using formal methods, e.g. equivalence checking or property checking
- G06F 30/347: Physical level, e.g. placement or routing
- G06F 30/39: Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347)
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A semiconductor memory device is provided. The semiconductor memory device includes a plurality of memory cells arranged in multiple column groups, each column group having, a plurality of columns and a plurality of external bit-lines for independent multi-way configurable access. The column group having a first, second, and third level of hierarchy in the external bit-lines. The first level of the hierarchy provides connectivity to the plurality of memory cells. The second level of the hierarchy provides a first splicer for multiplexing data to and from each of the columns in the column group to an intermediate bit-line. The third level of the hierarchy includes a second splicer for multiplexing data to and from multiple external access paths to the intermediate bit-line. A structurally reconfigurable circuit device and methods for designing a circuit are also provided.

## Claims

### Claim 1

A structurally reconfigurable semiconductor circuit device for in-memory processing of stateful, transaction-oriented applications, comprising:
a multiple level array of memory storage cells and logic circuits, the storage cells having multiple configurable access paths, the storage cells capable of being simultaneously accessed for being read from and written into;
a plurality of configurable, packetized interface ports capable of receiving data packets, the packetized interface ports having access to the multiple level array;
a plurality of configurable commute elements distributed within the multiple level array, each of the plurality of configurable commute element configured to move data within the multiple level array of storage cells through one of the multiple configurable access paths;
a plurality of configurable Compute elements within the multiple level array, each of the plurality of configurable Compute elements configured to transform data within a portion of the multiple level array of storage cells via the multiple configurable access paths; and
a pool of redundant features for repairing a defective feature within the multiple level array, wherein levels of the multiple level array associated with a higher defect density have more redundant features available for repair relative to levels associated with a lower defect density.

### Claim 2 (depends on 1)

The device of claim 1 further comprising:
configuration cells hard wired to one of a first or a second logic state.

### Claim 3 (depends on 1)

The device of claim 1 further comprising:
a read access path coupled to the memory storage cells to enable a non-destructive read.

### Claim 4 (depends on 1)

The device of claim 1 further comprising:
a metal-insulator-metal capacitor provided to increase a charge of a corresponding memory storage cell thereby providing enhanced soft error resiliency.

### Claim 5 (depends on 1)

The device of claim 1 further comprising:
an electro-magnetic interference (EMI) reduction apparatus, the EMI reduction apparatus including:
a clock distribution tree such that clock signals between portions of the multiple level array is skewed with respect to one another and wherein contemporaneous access to the memory storage cells is provided through skewed clocks on different read and write access paths.

### Claim 6 (depends on 1)

The device of claim 1 wherein an interface port has access to a storage cell within the multiple level array according to an asynchronous clock that is independent of clocks on other access paths to the storage cell.

### Claim 7 (depends on 1)

The device of claim 1 wherein a refresh for a memory storage cell within the multiple level array occurs over one of the multiple configurable access paths and is applied selectively to portions of the multiple level array.

### Claim 8 (depends on 1)

The device of claim 1 wherein the storage cells are selected from a group consisting of a volatile random access memory (SRAM), a dynamic random access memory (DRAM) and a non-volatile memory.

### Claim 9 (depends on 1)

The device of claim 1 wherein the storage cells are accessed for read and write in a time-multiplexed fashion.

### Claim 10 (depends on 7)

The device of claim 7 wherein the refresh is performed transparently by dedicated logic.

### Claim 11 (depends on 1)

The device of claim 1, wherein the device is capable of being configured to express a stateful, transaction-oriented application as a network of FlowVirtualMachines (FVMs) having an arbitrary number of memory storage cells asigned to the application, wherein multiple FVMs are capable of being linearly composed into an AggregateFlowVirtualMachine (AFVM), and wherein the AFVM is mapped into a FlowTile of the multiple level array.

### Claim 12 (depends on 1)

The device of claim 1, wherein the device is included in a multi-chip module package.

### Claim 13 (depends on 12)

The device of claim 12, wherein the multi-chip module package includes a mixed signal companion die for serializing one of the plurality of packetized interface ports to a serial interface.

### Claim 14 (depends on 1)

The device of claim 1, wherein the plurality of configurable commute elements and the plurality of configurable Compute elements are physically bit-aligned to portions of the multiple level array.

### Claim 15 (depends on 1)

The device of claim 1, wherein the memory cells are one of a flip flop, latch, or a capacitor.

### Claim 16

A structurally reconfigurable semiconductor circuit device for in-memory processing of stateful, transaction-oriented applications, comprising:
a multiple level array of memory storage cells and logic circuits, the storage cells having multiple configurable access paths, the storage cells capable of being simultaneously accessed for being read from and written into;
a plurality of configurable, packetized interface ports capable of receiving data packets, the packetized interface ports having access to the multiple level array;
a plurality of configurable commute elements distributed within the multiple level array, each of the plurality of configurable commute element configured to move data within the multiple level array of storage cells through one of the multiple configurable access paths;
a plurality of configurable Compute elements within the multiple level array, each of the plurality of configurable Compute elements configured to transform data within a portion of the multiple level array of storage cells via the multiple configurable access paths; wherein the device is capable of being configured to express a stateful, transaction-oriented application as a network of FlowVirtualMachines (FVMs) having an arbitrary number of memory storage cells asigned to the application, wherein multiple FVMs are capable of being linearly composed into an AggregateFlowVirtualMachine (AFVM), and wherein the AFVM is mapped into a FlowTile of the multiple level array.

### Claim 17 (depends on 1)

The device of claim 1, further comprising:
a pool of redundant features for repairing a defective feature within the multiple level array, wherein levels of the multiple level array associated with a higher defect density have more redundant features available for repair relative to levels associated with a lower defect density.