# US 7,613,974 B2 · Fault detection method and apparatus

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- Number: US 7,613,974 B2
- Document ID: US7613974B2
- Status: Granted
- Kind: B2
- Application number: 11/689,224
- Filed: 2007-03-21
- Published: 2007-11-29
- Granted: 2009-11-03
- Earliest claimed: 2006-03-24
- Assignees: ICS Triplex Technology Ltd.
- Inventors: Thomas Bruce Meagher
- Web page: https://patentgrep.com/patent/US7613974B2

## CPC

- G01R 31/318516: {Test of programmable logic devices [PLDs]}
- G01R 31/318536: {Scan chain arrangements, e.g. connections, test bus, analog signals}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)

## Abstract

This invention relates to fault detection in electrical circuits. The invention provides a method and apparatus for testing an input circuit by generating a periodic test signal having a predetermined phase and a predetermined amplitude; summing the test signal and an input signal to provide a summed signal; processing the summed signal to provide an output signal; generating an extracted test signal from the output signal; comparing the extracted test signal with a reference signal representing said periodic test signal; generating an error signal in dependence upon the result of said comparing step. The invention also provides a method and apparatus for testing a plurality of adjacent input circuits.

## Claims

### Claim 1

A method of testing an input circuit comprising the steps of:
generating a test signal which is periodic and has a predetermined phase and a predetermined amplitude;
summing the test signal and an input signal to provide a summed signal;
processing the summed signal with the input circuit to provide an output value;
processing the output value to provide an output signal corresponding to the input signal;
generating an extracted test signal from the output value corresponding to the test signal;
comparing the extracted test signal with a reference signal representing said test signal;
generating an error signal in dependence upon the result of said comparing step;
whereby testing of the input circuit can be obtained during operation of the input circuit with the input signal.

### Claim 2 (depends on 1)

The method according to claim 1, in which the test signal comprises a symmetrical signal having a test signal period and in which the output signal is produced by sampling the output value at intervals of a sample period and averaged over a moving average period equal to an integer multiple of the test signal period and in which the sample period is such that the average value of the contribution from the symmetrical test signal over said moving average period is equal to zero.

### Claim 3 (depends on 2)

The method according to claim 2, in which the test signal is a sinusoidal signal.

### Claim 4 (depends on 2)

The method according to claim 2, in which the moving average period is equal to the test signal period.

### Claim 5 (depends on 4)

The method according to claim 4, in which the test signal period is 4 ms; the sample period is 1 ms, and an average of the previous four samples is generated every 1 ms.

### Claim 6 (depends on 1)

The method in which a plurality of independent input circuits are tested according to the method of claim 1 and in which a plurality of test signals are generated by the steps of:
generating a digital representation of a the test signal, the digital representation comprising a number of bits equal to the number of test signals to be generated;
storing said digital representation in a shift register;
generating a plurality of digital test signals from a plurality of taps from the shift register such that each digital test signal comprises a uniquely phased digital pattern;
low pass filtering each digital test signal to generate a plurality of unique analogue test signals.

### Claim 7 (depends on 6)

The method according to claim 6, in which a first test signal used to test a first input circuit is arranged to have as great a phase separation as possible from a second test signal used to test a second adjacent input circuit.

### Claim 8

An apparatus for testing an input circuit comprising:
means for generating a test signal which is periodic and has a predetermined phase and a predetermined amplitude;
an adder for summing the test signal and an input signal to provide a summed signal;
means for processing the summed signal with the input circuit to provide an output value;
means for processing the output value to provide an output signal corresponding to the input signal;
means for generating an extracted test signal value corresponding to the test signal;
a comparator for comparing the extracted test signal with a reference signal representing said test signal and for generating an error signal in dependence upon said comparison.