# US 7,613,967 B1 · Inversion of scan clock for scan cells

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- Number: US 7,613,967 B1
- Document ID: US7613967B1
- Status: Granted
- Kind: B1
- Application number: 12/290,262
- Filed: 2008-10-29
- Granted: 2009-11-03
- Earliest claimed: 2004-07-29
- Assignees: Marvell International Ltd.
- Inventors: Teck Wee Patrick Tan
- Web page: https://patentgrep.com/patent/US7613967B1

## CPC

- G01R 31/318541: {Scan latches or cell details}
- G01R 31/318594: {Timing aspects (clock circuits G01R31/318552)}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)

## Abstract

A device includes a scan circuit including a scan chain. The scan chain includes a first plurality of scan cells that receive a first scan clock signal in a first clock domain. A second plurality of scan cells receives a second scan clock signal in a second clock domain. A scan clock source generates the first scan clock signal and the second scan clock signal, and selectively inverts the first scan clock signal and the second scan clock signal based on an operating mode of the first plurality of scan cells and the second plurality of scan cells, respective flip-flop arrangements of the first clock domain and the second clock domain.

## Claims

### Claim 1

A device comprising:
a scan circuit including a scan chain, the scan chain having
a first plurality of scan cells that receive a first scan clock signal in a first clock domain; and
a second plurality of scan cells that receive a second scan clock signal in a second clock domain; and
a scan clock source that generates the first scan clock signal and the second scan clock signal, and that selectively inverts the first scan clock signal and the second scan clock signal based on
an operating mode of the first plurality of scan cells and the second plurality of scan cells; and
respective flip-flop arrangements of the first clock domain and the second clock domain.

### Claim 2 (depends on 1)

The device of claim 1, wherein a last scan cell of the first plurality of scan cells is directly connected to a first scan cell of the second plurality of scan cells.

### Claim 3 (depends on 1)

The device of claim 1, wherein:
each scan cell of the first plurality of scan cells and the second pluralities of scan cells includes a flip-flop; and
each flip-flop in the second plurality of scan cells is triggered before any flip-flop in the first plurality of scan cells.

### Claim 4 (depends on 1)

The device of claim 1, wherein:
a first scan cell in the first clock domain receives a scan-in signal based on the first scan clock signal; and
a last scan cell in the second clock domain generates a scan-out signal based on the second scan clock signal.

### Claim 5 (depends on 1)

The device of claim 1, wherein the scan clock source receives an external clock signal and generates the first scan clock signal and the second scan clock signal based on the external clock signal.

### Claim 6 (depends on 5)

The device of claim 5, wherein:
each scan cell of the first plurality of scan cells and the second plurality of scan cells includes a positive edge-triggered flip-flop; and
the first scan clock signal is inverted relative to the external clock signal.

### Claim 7 (depends on 5)

The device of claim 5, wherein:
each scan cell of the first plurality of scan cells and the second plurality of scan cells includes a negative edge-triggered flip-flop; and
the second scan clock signal is inverted relative to the external clock signal.

### Claim 8 (depends on 1)

The device of claim 1, wherein the scan circuit comprises a plurality of the scan chains.

### Claim 9 (depends on 1)

An integrated circuit (IC) comprising the device of claim 1.

### Claim 10

A method comprising:
receiving a first scan clock signal at a first plurality of scan cells in a first clock domain;
receiving a second scan clock signal at a second plurality of scan cells in a second clock domain;
generating the first scan clock signal and the second scan clock signal at a scan clock source; and
selectively inverting the first scan clock signal and the second scan clock signal based on
an operating mode of the first plurality of scan cells and the second plurality of scan cells; and
respective flip-flop arrangements of the first and second clock domains.

### Claim 11 (depends on 10)

The method of claim 10, further comprising directly connecting a last scan cell of the first plurality of scan cells to a first scan cell of the second plurality of scan cells.

### Claim 12 (depends on 10)

The method of claim 10, wherein:
each scan cell of the first plurality of scan cells and the second plurality of scan cells includes a flip-flop; and
each flip-flop in the second plurality of scan cells is triggered before any flip-flop in the first plurality of scan cells.

### Claim 13 (depends on 10)

The method of claim 10, further comprising:
receiving a scan-in signal at a first scan cell in the first clock domain based on the first scan clock signal; and
generating a scan-out signal at a last scan cell in the second clock domain based on the second scan clock signal.

### Claim 14 (depends on 10)

The method of claim 10, further comprising:
receiving an external clock signal; and
generating the first scan clock signal and the second scan clock signal based on the external clock signal.

### Claim 15 (depends on 14)

The method of claim 14, wherein:
each scan cell of the first plurality of scan cells and the second plurality of scan cells includes a positive edge-triggered flip-flop; and
the first scan clock signal is inverted relative to the external clock signal.

### Claim 16 (depends on 14)

The method of claim 14, wherein:
each scan cell of the first plurality of scan cells and the second plurality of scan cells includes a negative edge-triggered flip-flop; and
the second scan clock signal is inverted relative to the external clock signal.