# US 7,613,962 B2 · Semiconductor integrated circuit with full-speed data transition scheme for DDR SDRAM at internally doubled clock testing application > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,613,962 B2 - Document ID: US7613962B2 - Status: Granted - Kind: B2 - Application number: 12/220,063 - Filed: 2008-07-21 - Published: 2008-12-11 - Granted: 2009-11-03 - Earliest claimed: 2002-11-13 - Assignees: Etron Technology, Inc. - Inventors: Ming-Hung Wang - Web page: https://patentgrep.com/patent/US7613962B2 ## CPC - G11C 29/12015: {comprising clock generation or timing circuitry} - G11C 7/1066: {Output synchronization} - G11C 7/1078: {Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits} - G11C 7/109: {Control signal input circuits} - G11C 29/14: Implementation of control logic, e.g. test mode decoders - G11C 11/401: forming cells needing refreshing or charge regeneration, i.e. dynamic cells - G11C 2207/107: Serial-parallel conversion of data or prefetch - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract The present invention provides a circuit and a method for the full speed testing of semiconductor memory chips. The invention provides a full-speed data transition scheme for double data rate (DDR) synchronous dynamic random access memory (SDRAM). For high speed or double speed stress testing of DDR SDRAM, the internal clock is double the speed of the external clock. During high speed test, this causes the data to be written or presented to the data path two times. This invention provides a circuit and method for creating a full-speed data transition scheme to overcome this double speed testing problem. ## Claims ### Claim 1 A semiconductor integrated circuit with full-speed data transition scheme for double data rate (DDR) synchronous dynamic random access memory (SDRAM) at internally doubled clock testing application comprising: a pulse generator having an output attached to a clear input of a toggle flip-flop, and having an input which is a write line from a memory controller, said toggle flip-flop having a data input coupled to an inverse output through a feedback of said flip-flop, wherein said toggle flip-flop further having a clock input, and a true output, an exclusive -OR circuit having one input which comes from said true output of said toggle flip-flop, having another whose input which is a select signal and having an output which is an external select signal, and a multiplexer circuit having one input which is the positive data input-bit, having another input which is the negative data-input bit which is the inverse of said positive data input bit, having a select line which is said external select line from said exclusive-OR circuit, having one output which is a data input-even bit and having another output which is a data input-odd bits, wherein said integrated circuit provides full-speed testing of said synchronous dynamic random access memory (SDRAM). ### Claim 2 (depends on 1) The semiconductor integrated circuit with full-speed data transition scheme of claim 1 wherein said pulse generator is used for generating a reset pulse each time said write input line goes active. ### Claim 3 (depends on 1) The semiconductor integrated circuit with full-speed data transition scheme of claim 1 wherein said exclusive-OR circuit produces an external select whenever said toggle output and said select input are of different logic levels. ### Claim 4 (depends on 1) The semiconductor integrated circuit with full-speed data transition scheme of claim 1 wherein said toggle flip-flop has a data input, which is fed from said inverse output causing said true output to toggle or to go from one voltage level to another. ### Claim 5 (depends on 1) The semiconductor integrated circuit with full-speed data transition scheme of claim 1 wherein said multiplexer transfers said positive data-input bits to said data-in even and transfers said negative data input bits to said data-in odd, where said select input32 0. ### Claim 6 (depends on 1) The semiconductor integrated circuit with full-speed data transition scheme of claim 1 wherein said multiplexer transfer, positive data input bits to said data-in odd bits, and transfer said negative data input bits to said data-in even bits, when said select signal32 1. ### Claim 7 (depends on 1) The semiconductor integrated circuit with full-speed data transition scheme of claim 1 wherein interface signals between said memory controller has two major interface signals to the double data rate synchronous dynamic random access memory (DDR SDRAM), a data strobe and said data bus. ### Claim 8 (depends on 1) The semiconductor integrated circuit with full-speed data transition scheme of claim 1 wherein said data strobe signal is used to latch or capture the data bit signal on the rising edge of said data strobe signal. ### Claim 9 (depends on 1) The semiconductor integrated circuit with full-speed data transition scheme of claim 1 wherein said data strobe signal is inverted and used to latch or capture the data bit signal on the falling edge of said data strobe signal. ### Claim 10 (depends on 1) The semiconductor integrated circuit with full-speed data transition scheme of claim 1 wherein said data strobe signal is inverted and used to latch or capture said output of said previously latched data bit signal on the falling edge of said data strobe signal. ### Claim 11 A method of designing a semiconductor integrated circuit with full-speed data transition scheme for double data rate (DDR) synchronous dynamic random access memory (SDRAM) at internally doubled clock testing application comprising the steps of: including a pulse generator having an output attached to a clear input of a toggle flip-flop, and having an input which is a write line from a memory controller, wherein said toggle flip-flop having a data input coupled to an inverse output through a feedback of said flip-flop, said toggle flip-flop further having a clock input, and a true output, including an exclusive -OR circuit having one input which comes from said true output of said toggle flip-flop, having another input which is a select signal and having an output which is an external select signal, and including a multiplexer circuit having one input which is the positive data input-bit, having another input which is the negative data-input bit, which is the inverse of said positive data input bit, having a select line which is said external select line from said exclusive-OR circuit, having one output which is a data input-even bit and having another output which is a data input-odd bits wherein said integrated circuit provides full-speed testing of said synchronous dynamic random access memory (SDRAM). ### Claim 12 (depends on 11) The method of designing a semiconductor integrated circuit with full-speed data transition scheme of claim 11 wherein said pulse generator is used for generating a reset pulse each time said write input line goes active. ### Claim 13 (depends on 11) The method of designing a semiconductor integrated circuit with full-speed data transition scheme of claim 11 wherein said exclusive-OR circuit produces an external select whenever said toggle output and said select input are of different logic levels. ### Claim 14 (depends on 11) The method of designing a semiconductor integrated circuit with full-speed data transition scheme of claim 11 wherein said toggle flip-flop has a data input, which is fed from said inverse output causing said true output to toggle or to go from one voltage level to another. ### Claim 15 (depends on 11) The method of designing a semiconductor integrated circuit with full-speed data transition scheme of claim 11 wherein said multiplexer transfers said positive data input positive bits to said data-in even and transfers said negative data input bits to said data-in odd, where said select input32 0. ### Claim 16 (depends on 11) The method of designing a semiconductor integrated circuit with full-speed data transition scheme of claim 11 wherein said multiplexer transfer, said positive data input bits to said data-in odd bits, and transfer said negative data input to said data-in even bits, when said select signal32 1. ### Claim 17 (depends on 11) The method of designing a semiconductor integrated circuit with full-speed data transition scheme of claim 11 wherein interface signals between said memory controller has two major interface signals to the double data rate synchronous dynamic random access memory (DDR SDRAM), a data strobe and said data bus. ### Claim 18 (depends on 11) The method of designing a semiconductor integrated circuit with full-speed data transition scheme of claim 11 wherein said data strobe signal is used to latch or capture the data bit signal on the rising edge of said data strobe signal. ### Claim 19 (depends on 11) The method of designing a semiconductor integrated circuit with full-speed data transition scheme of claim 11 wherein said data strobe signal is inverted and used to latch or capture the data bit signal on the falling edge of said data strobe signal. ### Claim 20 (depends on 11) The method of designing a semiconductor integrated circuit with full-speed data transition scheme of claim 11 wherein said data strobe signal is inverted and used to latch or capture said output of said previously latched data bit signal on the falling edge of said data strobe signal.