# US 7,613,961 B2 · CPU register diagnostic testing > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,613,961 B2 - Document ID: US7613961B2 - Status: Granted - Kind: B2 - Application number: 10/685,177 - Filed: 2003-10-14 - Published: 2005-04-14 - Granted: 2009-11-03 - Earliest claimed: 2003-10-14 - Assignees: Hewlett-Packard Development Company, L.P. - Inventors: Andrew Harvey Barr; Ken Gary Pomaranski; Dale John Shidla - Web page: https://patentgrep.com/patent/US7613961B2 ## CPC - G06F 11/263: Generation of test inputs, e.g. test vectors, patterns or sequences {; with adaptation of the tested hardware for testability with external testers} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract One embodiment disclosed relates to a method of compiling a program to be executed on a target central processing unit (CPU). The method includes opportunistically scheduling diagnostic testing of CPU registers. The method may include use of a predetermined level of aggressiveness for the scheduling of the register diagnostic testing. The scheduled diagnostic testing may include writing known data to a register, reading data from the register, and comparing the known data with the data that was read. If the comparison indicates a difference, then a jump may occur to a fault handler routine. ## Claims ### Claim 1 A method for testing a central processing unit (CPU) register, the method comprising: scheduling user code instructions during a compiling of a software program to be executed on a target CPU; and opportunistically scheduling diagnostic testing of CPU registers during said compiling so that testing of the CPU registers occurs within normal running of the user code instructions during execution of the program after said compiling, wherein all of the CPU registers are scheduled for some level of diagnostic testing, the opportunistically scheduling diagnostic testing comprising: checking a predetermined level of aggressiveness for the scheduling of a register diagnostic; determining a next register to be tested; determining if there is sufficient opportunity to schedule a register diagnostic instruction to test the next register without substantially impacting performance of the program, wherein if there is the sufficient opportunity, then scheduling the register diagnostic instruction to test the next register, and if there is insufficient opportunity to schedule the register diagnostic instruction, then scheduling the user code instructions; and if an error in a CPU register of the CPU registers is indicated, jumping to a fault handler routine. ### Claim 2 (depends on 1) The method of claim 1, wherein the CPU registers comprise registers in a general register file. ### Claim 3 (depends on 1) The method of claim 1, wherein the scheduled diagnostic testing includes writing known data to a register, reading data from the register, and comparing the known data with the data that was read. ### Claim 4 (depends on 3) The method of claim 3, wherein if the comparison indicates a difference, then said jump to the fault handler routine is performed. ### Claim 5 (depends on 4) The method of claim 4, wherein the fault handler routine is configured to halt execution to avoid potential data corruption. ### Claim 6 (depends on 4) The method of claim 4, wherein the fault handler routine is configured to remap activity to the register to an alternate register. ### Claim 7 A method for testing central processing unit (CPU) registers, the method comprising: opportunistically scheduling diagnostic testing of CPU registers, wherein all of the CPU registers are scheduled for some level of diagnostic testing, the opportunistically scheduling diagnostic testing comprising: checking a predetermined level of aggressiveness for the scheduling of the register diagnostic testing; determining a next register to be tested; determining if there is sufficient opportunity to schedule a register diagnostic instruction to test the next register without substantially impacting performance of a program; if there is sufficient opportunity, then scheduling the register diagnostic instruction to test the next register; and if there is insufficient opportunity, then scheduling user code instructions. ### Claim 8 A computer-readable medium embedded with a compiler program for execution on a target microprocessor, the computer-readable medium comprising: executable code configured for scheduling user code instructions; and executable code configured for opportunistically scheduling diagnostic testing of registers in the microprocessor so that testing of the registers occurs within normal running of the user code instructions and all of the CPU registers are scheduled for some level of diagnostic testing, wherein the executable code for opportunistically scheduling diagnostic testing comprises: executable code for checking a predetermined level of aggressiveness for the scheduling of the register diagnostic testing; executable code for determining a next register to be tested; executable code for determining if there is sufficient opportunity to schedule a register diagnostic instruction to test the next register without substantially impacting performance of the compiler program; executable code for scheduling the register diagnostic instruction to test the next register if there is sufficient opportunity; and executable code for scheduling user code instructions if there is insufficient opportunity to schedule the register diagnostic; and executable code configured for jumping to a fault handler routine if an error in the register is indicated. ### Claim 9 (depends on 8) The computer-readable medium of claim 8, wherein the scheduled diagnostic testing includes writing known data to a register, reading data from the register, and comparing the known data with the data that was read. ### Claim 10 (depends on 9) The computer-readable medium of claim 9, wherein if the comparison indicates a difference, then said jump occurs to said fault handler routine. ### Claim 11 (depends on 10) The computer-readable medium of claim 10, wherein the fault handler routine is configured to halt execution to avoid potential data corruption. ### Claim 12 (depends on 10) The computer-readable medium of claim 10, wherein the fault handler routine is configured to remap activity to the register to an alternate register. ### Claim 13 (depends on 8) The computer-readable program product of claim 8, wherein the aggressiveness level is set at a high level, and wherein the diagnostic testing is scheduled to be performed periodically.