# US 7,613,950 B2 · Detecting floating point hardware failures > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,613,950 B2 - Document ID: US7613950B2 - Status: Granted - Kind: B2 - Application number: 10/789,733 - Filed: 2004-02-27 - Published: 2005-09-15 - Granted: 2009-11-03 - Earliest claimed: 2004-02-27 - Assignees: Hewlett-Packard Development Company, L.P. - Inventors: John W. Curry - Web page: https://patentgrep.com/patent/US7613950B2 ## CPC - G06F 11/2236: {to test CPU or processors} - G06F 11/1487: using N-version programming - G06F 11/1497: Time redundant execution of software on a single processing unit - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A method for testing floating point hardware in a processor while executing a computer program is disclosed. The method includes executing a first set of code of the computer program without employing the floating point hardware. The first set of code has a first floating point operation, thereby obtaining an emulated result. The method also includes executing the first floating point instruction utilizing the floating point hardware, thereby obtaining a hardware-generated result. The method also includes comparing the emulated result with the hardware-generated result. ## Claims ### Claim 1 A method for testing floating point hardware in a processor while executing a computer program, comprising: executing a first set of code of said computer program without employing said floating point hardware, said first set of code having a first floating point instruction, thereby obtaining an emulated result; executing said first floating point instruction utilizing said floating point hardware, thereby obtaining a hardware-generated result; and comparing said emulated result with said hardware-generated result. ### Claim 2 (depends on 1) The method of claim 1 further comprising rendering said floating point hardware unavailable prior to said executing said first set of code of said computer program without employing said floating point hardware. ### Claim 3 (depends on 2) The method of claim 2 wherein said processor represents an Itanium™ processor, said rendering said floating point hardware unavailable including setting at least one of a DFH and a DEL bit in a processor status register of said processor. ### Claim 4 (depends on 2) The method of claim 2 wherein said processor represents a PA-RISC™ processor, said rendering said floating point hardware unavailable including clearing a CR10 co-processor control register of said processor. ### Claim 5 (depends on 2) The method of claim 2 wherein said rendering said floating point hardware unavailable includes writing a first predefined value into a register in said processor. ### Claim 6 (depends on 5) The method of claim 5 further comprising rendering said floating point hardware available for executing instructions of said computer program prior to said executing said first floating point instruction utilizing said floating point hardware. ### Claim 7 (depends on 6) The method of claim 6 wherein said rendering said hardware available includes writing a second predefined value into said register in said processor. ### Claim 8 (depends on 7) The method of claim 7 wherein said processor represents an Itanium™ processor, said rendering said floating point hardware available including clearing at least one of a DFH and a DEL bit in a processor status register of said processor. ### Claim 9 (depends on 7) The method of claim 7 wherein said processor represents a PA-RISC™ processor, said rendering said floating point hardware available including setting a CR10 co-processor control register of said processor. ### Claim 10 (depends on 1) The method of claim 1 wherein said obtaining said hardware-generated result includes obtaining a trap result after said first floating point instruction is executed utilizing said floating point hardware. ### Claim 11 (depends on 1) The method of claim 1 wherein said obtaining said emulated result includes obtaining a hardware-generated trap result after said processor encounters said first floating point instruction while said floating point hardware is unavailable. ### Claim 12 (depends on 1) The method of claim 1 wherein said computer program represents a field application program. ### Claim 13 A method for detecting failure in floating point hardware of a processor while executing a computer program, comprising: entering a diagnostic mode, including executing a first floating point operation of said computer program by emulating said floating point operation with a set of non-floating point operations, thereby obtaining an emulated result, executing said first floating point operation utilizing said floating point hardware, thereby obtaining a hardware-generated result, and comparing said emulated result with said hardware-generated result to detect said failure to detect said failure; determining whether diagnostic mode is to be continued; and resuming execution of said computer program in a non-diagnostic mode if said diagnostic mode is to be discontinued, said non-diagnostic mode involving performing floating point operations of said computer program without emulating with non-floating point operations. ### Claim 14 (depends on 13) The method of claim 13 said entering said diagnostic mode further comprising rendering said floating point hardware unavailable prior to said executing said first floating point operation by said emulating. ### Claim 15 (depends on 14) The method of claim 14 wherein said processor represents an Itanium™ processor, said rendering said floating point hardware unavailable including setting at least one of a DFH and a DEL bit in a processor status register of said processor. ### Claim 16 (depends on 14) The method of claim 14 wherein said processor represents a PA-RISC™ processor, said rendering said floating point hardware unavailable including clearing a CR10 co-processor control register of said processor. ### Claim 17 (depends on 14) The method of claim 14 wherein said rendering said floating point hardware unavailable includes writing a first predefined value into a register in said processor. ### Claim 18 (depends on 17) The method of claim 17 wherein said entering said diagnostic mode further including rendering said floating point hardware available for executing instructions of said computer program prior to said executing said first floating point operation utilizing said floating point hardware. ### Claim 19 (depends on 18) The method of claim 18 wherein said rendering said hardware available includes writing a second predefined value into said register in said processor. ### Claim 20 (depends on 19) The method of claim 19 wherein said processor represents an Itanium™ processor, said rendering said floating point hardware available including clearing at least one of a DFH and a DFL bit in a processor status register of said processor. ### Claim 21 (depends on 19) The method of claim 19 wherein said processor represents a PA-RISC™ processor, said rendering said floating point hardware available including setting a CR10 co-processor control register of said processor. ### Claim 22 (depends on 13) The method of claim 13 wherein said obtaining said hardware-generated result includes obtaining a trap after said first floating point operation is executed utilizing said floating point hardware. ### Claim 23 An article of manufacture comprising a program storage medium having computer readable code embodied therein, said computer readable code being configured to test floating point hardware in a processor while executing a computer program, comprising: computer readable code for executing a first set of code of said computer program without employing said floating point hardware, said first set of code having a first floating point instruction, thereby obtaining an emulated result; computer readable code for executing said first floating point instruction utilizing said floating point hardware, thereby obtaining a hardware-generated result; and computer readable code for comparing said emulated result with said hardware-generated result. ### Claim 24 (depends on 23) The article of manufacture of claim 23 further comprising computer readable code for rendering said floating point hardware unavailable prior to said executing said first set of code of said computer program without employing said floating point hardware. ### Claim 25 (depends on 24) The article of manufacture of claim 24 wherein said computer readable code for rendering said floating point hardware unavailable includes computer readable code for writing a first predefined value into a register in said processor. ### Claim 26 (depends on 25) The article of manufacture of claim 25 further comprising computer readable code for rendering said floating point hardware available for executing instructions of said computer program prior to said executing said first floating point instruction utilizing said floating point hardware. ### Claim 27 (depends on 26) The article of manufacture of claim 26 wherein said computer readable code for rendering said hardware available includes computer readable code for writing a second predefined value into said register in said processor.