# US 7,613,948 B2 · Cache coherency during resynchronization of self-correcting computer > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,613,948 B2 - Document ID: US7613948B2 - Status: Granted - Kind: B2 - Application number: 12/033,408 - Filed: 2008-02-19 - Published: 2008-06-12 - Granted: 2009-11-03 - Earliest claimed: 2003-02-28 - Assignees: Maxwell Technologies, Inc. - Inventors: Robert A. Hillman; Mark Steven Conrad - Web page: https://patentgrep.com/patent/US7613948B2 ## CPC - G06F 11/184: {where the redundant components implement processing functionality} - G06F 11/1658: {Data re-synchronization of a redundant component, or initial sync of replacement, additional or spare unit} - G06F 11/1687: {at event level, e.g. by interrupt or result of polling} - G06F 11/1691: {using a quantum} - G06F 11/181: {Eliminating the failing redundant component} - G06F 11/00: Error detection; Error correction; Monitoring (error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00) - G06F 11/1666: {where the redundant component is memory or memory area} - G06F 11/1679: {at clock signal level} - G06F 11/187: {Voting techniques} - G06F 11/20: using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements - G06F 2201/81: Threshold - G06F 2201/88: Monitoring involving counting - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A fault-tolerant computer uses multiple commercial processors operating synchronously, i.e., in lock-step. In an exemplary embodiment, redundancy logic isolates the outputs of the processors from other computer components, so that the other components see only majority vote outputs of the processors. Processor resynchronization, initiated at predetermined time, milestones, and/or in response to processor faults, protects the computer from single event upsets. During resynchronization, processor state data is flushed and an instance of these data in accordance with processor majority vote is stored. Processor caches are flushed to update computer memory with more recent data stored in the caches. The caches are invalidated and disabled, and snooping is disabled. A controller is notified that snooping has been disabled. In response to the notification, the controller performs a hardware reset of the processors. The processors are loaded with the stored state data, and snooping and caches are enabled. ## Claims ### Claim 1 The method of operating a fault-tolerant computer system with at least three processors, comprising steps of: flushing out internal processor state data from processors of the plurality of processors; determining an instance of the flushed out internal processor state data in accordance with processor majority vote; storing the instance; invalidating and disabling caches of the processors of the plurality of processors; disabling snooping; holding each processor of the plurality of processors with the instance; enabling snooping; enabling the caches of the processors of the plurality of processors; and synchronously operating all processors of the at least three processors in parallel while determining processor majority vote of processor output signals; wherein the step of enabling snooping is performed after initialization of the memory management units of the at least three processors following the step of holding. ### Claim 2 (depends on 1) The method of claim 1, further comprising: flushing out the caches of the processors of the plurality of processors between the step of flushing out internal processor state data from processors of the plurality of processors and the step of invalidating. ### Claim 3 (depends on 1) The method of claim 1, wherein the step of flushing out internal processor state data is performed at predetermined times. ### Claim 4 (depends on 1) The method of claim 1, wherein the step of flushing out internal processor state data is performed at predetermined milestones. ### Claim 5 (depends on 1) The method of claim 1, wherein the step of flushing out internal processor state data is performed at predetermined milestones of at least one software application executed by the computer system. ### Claim 6 (depends on 1) The method of claim 1, wherein the step of flushing out internal processor state data is performed in response to a single event upset in at least one processor of the plurality of processors. ### Claim 7 (depends on 1) The method of claim 1, wherein the step of flushing out internal processor state data is performed at predetermined intervals, further comprising: shortening at least one of the intervals in response to an error in at least one processor of the plurality of processors. ### Claim 8 (depends on 1) The method of claim 1, wherein the step of flushing out internal processor state data is performed in response to loss of synchronization of a first processor of the plurality of processors with respect to at least a second processor and a third processor of the plurality of processors. ### Claim 9 (depends on 1) The method of claim 1, wherein the instance does not include data stored in the caches of the processors of the plurality of processors. ### Claim 10 (depends on 1) The method of claim 1, wherein the instance includes all internal processor state data other than cache data stored in the caches of the processors of the plurality of processors. ### Claim 11 A method of using a fault-tolerant computer system comprising at least three processors operating synchronously in parallel, wherein each processorr of the at least three processors comprise a memory management unit (MMU), the method comprising: operating the at least three processors with enabled snooping by external devices; step for processor resynchronization of the at least three processors; and step for preventing snooping by the external devices while the at least three processors are coming out of reset caused by the step for processor resynchronization, wherein the step fro preventing is performed until initialization of the memory management units of the at least three processors. ### Claim 12 (depends on 11) The method of claim 11, wherein the step for processor resynchronization is performed after the step of operating. ### Claim 13 (depends on 11) The method of claim 11, wherein the step for processor resynchronization is performed in response to a single event upset in the at least three processors. ### Claim 14 (depends on 11) The method of claim 11, wherein the step for processor resynchronization is performed at predetermined times. ### Claim 15 (depends on 11) The method of claim 11, wherein the step for processor resynchronization is performed at predetermined milestones. ### Claim 16 A method of operating a fault-tolerant computer system comprising a plurality of processors operating in lock-step, the method comprising: resynchronizing the processors; preventing bus transactions while the processors of the plurality of processors are coming out of reset caused by the step of resynchronizing; wherein the step of preventing comprises bypassing snooping, and the step of preventing is performed at least until initialization of memory management units (MMUs) of the processors.