# US 7,613,944 B2 · Programmable local clock buffer capable of varying initial settings > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,613,944 B2 - Document ID: US7613944B2 - Status: Granted - Kind: B2 - Application number: 11/609,403 - Filed: 2006-12-12 - Published: 2008-06-12 - Granted: 2009-11-03 - Earliest claimed: 2006-12-12 - Assignees: International Business Machines Corporation - Inventors: Yuen H. Chan; Michael J. Lee - Web page: https://patentgrep.com/patent/US7613944B2 ## CPC - G06F 1/10: Distribution of clock signals {, e.g. skew} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A programmable local clock buffer for integrated circuit devices which is capable of varying initial settings is provided. The illustrative embodiments allow a single type of local clock buffer (LCB) to be used throughout an integrated circuit design while still being able to provide differing initial offsets and pulse widths for different local circuitry portions of the integrated circuit design. Delay circuit paths are provided, which provide discreet delay values, within the LCB that can be chained together when the LCB is instantiated to set the initial offset and pulse width values. When an LCB is instantiated in the integrated circuit device design, various ones of the delay circuit paths are connected together with the existing circuit paths of the LCB, i.e. the circuit paths that provide the pre-established offset and pulse width values, in order to set the initial offset and pulse width values for the LCB. ## Claims ### Claim 1 A method, in a data processing system, for providing an integrated circuit, comprising: receiving an integrated circuit design; providing a local clock buffer in association with a local portion of the integrated circuit design; providing one or more delay circuit paths, the one or more delay circuit paths being selectively connectable to existing circuit paths in the local clock buffer; configuring the local clock buffer to use one of the existing circuit paths in the local clock buffer to obtain a pre-established initial clock signal characteristic for converting an input clock signal to a local clock signal output; and selectively connecting the existing circuit path used by the local clock buffer to at least one of the one or more delay circuit paths to thereby modify the pre-established initial clock signal characteristic to thereby provide a modified initial clock signal characteristic for the local clock signal output. ### Claim 2 (depends on 1) The method of claim 1, wherein the local clock buffer receives a clock input signal from a clock signal grid of the integrated circuit design and provides the local clock signal output to the local portion of the integrated circuit design. ### Claim 3 (depends on 1) The method of claim 1, wherein the pre-established initial clock signal characteristic is a pulse width of the initial clock signal, and wherein the modified initial clock signal characteristic is a modified pulse width of the initial clock signal. ### Claim 4 (depends on 1) The method of claim 1, wherein the initial clock signal characteristic is an offset of the initial clock signal, and wherein the modified initial clock signal characteristic is a modified offset of the initial clock signal. ### Claim 5 (depends on 1) The method of claim 1, wherein a plurality of local clock buffers are provided, each local clock buffer in the plurality of local clock buffers utilizes a same circuit element to represent the local clock buffers, and wherein at least two of the plurality of local clock buffers have differing connections to the one or more delay circuit paths to thereby provide at least two local clock buffers that provide differing local clock signal outputs. ### Claim 6 (depends on 5) The method of claim 5, wherein the one or more delay circuit paths are provided as part of the circuit element. ### Claim 7 (depends on 5) The method of claim 5, wherein the one or more delay circuit paths are provided as a user-specific separate logic block that is selectively added to the circuit elements representing the local clock buffers which do not include the one or more delay paths. ### Claim 8 A computer program product comprising a computer readable storage medium having a computer readable program, wherein the computer readable program, when executed on a computing device, causes the computing device to: receive an integrated circuit design; provide a local clock buffer in association with a local portion of the integrated circuit design; provide one or more delay circuit paths, the one or more delay circuit paths being selectively connectable to existing circuit paths in the local clock buffer; configure the local clock buffer to use one of the existing circuit paths in the local clock buffer to obtain a pre-established initial clock signal characteristic for converting an input clock signal to a local clock signal output; and selectively connect the existing circuit path used by the local clock buffer to at least one of the one or more delay circuit paths to thereby modify the pre-established initial clock signal characteristic to thereby provide a modified initial clock signal characteristic for the local clock signal output. ### Claim 9 (depends on 8) The computer program product of claim 8, wherein the local clock buffer receives a clock input signal from a clock signal grid of the integrated circuit design and provides the local clock signal output to the local portion of the integrated circuit design. ### Claim 10 (depends on 8) The computer program product of claim 8, wherein the pre-established initial clock signal characteristic is a pulse width of the initial clock signal, and wherein the modified initial clock signal characteristic is a modified pulse width of the initial clock signal. ### Claim 11 (depends on 8) The computer program product of claim 8, wherein the initial clock signal characteristic is an offset of the initial clock signal, and wherein the modified initial clock signal characteristic is a modified offset of the initial clock signal. ### Claim 12 (depends on 8) The computer program product of claim 8, wherein a plurality of local clock buffers are provided, each local clock buffer in the plurality of local clock buffers utilizes a same circuit element to represent the local clock buffers, and wherein at least two of the plurality of local clock buffers have differing connections to the one or more delay circuit paths to thereby provide at least two local clock buffers that provide differing local clock signal outputs. ### Claim 13 (depends on 12) The computer program product of claim 12, wherein the one or more delay circuit paths are provided as part of the circuit element. ### Claim 14 (depends on 12) The computer program product of claim 12, wherein the one or more delay circuit paths are provided as a user-specific separate logic block that is selectively added to the circuit elements representing the local clock buffers which do not include the one or more delay paths. ### Claim 15 A data processing system, comprising: a processor; and a memory coupled to the processor, wherein the memory comprises instructions which, when executed by the processor, cause the processor to: receive an integrated circuit design; provide a local clock buffer in association with a local portion of the integrated circuit design; provide one or more delay circuit paths, the one or more delay circuit paths being selectively connectable to existing circuit paths in the local clock buffer; configure the local clock buffer to use one of the existing circuit paths in the local clock buffer to obtain a pre-established initial clock signal characteristic for converting an input clock signal to a local clock signal output; and selectively connect the existing circuit path used by the local clock buffer to at least one of the one or more delay circuit paths to thereby modify the pre-established initial clock signal characteristic to thereby provide a modified initial clock signal characteristic for the local clock signal output. ### Claim 16 (depends on 15) The system of claim 15, wherein the local clock buffer receives a clock input signal from a clock signal grid of the integrated circuit design and provides the local clock signal output to the local portion of the integrated circuit design. ### Claim 17 (depends on 15) The system of claim 15, wherein the pre-established initial clock signal characteristic is a pulse width of the initial clock signal, and wherein the modified initial clock signal characteristic is a modified pulse width of the initial clock signal. ### Claim 18 (depends on 15) The system of claim 15, wherein the initial clock signal characteristic is an offset of the initial clock signal, and wherein the modified initial clock signal characteristic is a modified offset of the initial clock signal. ### Claim 19 (depends on 15) The system of claim 15, wherein a plurality of local clock buffers are provided, each local clock buffer in the plurality of local clock buffers utilizes a same circuit element to represent the local clock buffers, and wherein at least two of the plurality of local clock buffers have differing connections to the one or more delay circuit paths to thereby provide at least two local clock buffers that provide differing local clock signal outputs. ### Claim 20 (depends on 19) The system of claim 19, wherein the one or more delay circuit paths are provided as part of the circuit element. ### Claim 21 (depends on 19) The system of claim 19, wherein the one or more delay circuit paths are provided as a user-specific separate logic block that is selectively added to the circuit elements representing the local clock buffers which do not include the one or more delay paths.