# US 7,613,941 B2 · Mechanism for self refresh during advanced configuration and power interface (ACPI) standard C0 power state > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,613,941 B2 - Document ID: US7613941B2 - Status: Granted - Kind: B2 - Application number: 11/323,344 - Filed: 2005-12-29 - Published: 2007-07-05 - Granted: 2009-11-03 - Earliest claimed: 2005-12-29 - Assignees: Intel Corporation - Inventors: Eric C. Samson; Robert Riesenman - Web page: https://patentgrep.com/patent/US7613941B2 ## CPC - G06F 13/1636: {using refresh} - G11C 11/406: Management or control of the refreshing or charge-regeneration cycles - G11C 11/40615: {Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs} - G11C 2211/4061: Calibration or ate or cycle tuning - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract An embodiment may be an apparatus comprising a link coupled with a memory, and circuitry coupled with the link to calculate the amount of memory access idle time, determine if memory access idle time is sufficient to change to a self-refresh state, and change to a self-refresh state based on memory access idle time without explicit notification from a processor regarding the processor power state. Another embodiment may be a method for memory to enter self-refresh comprising calculating the amount of memory access idle time, determining if memory access idle time is sufficient to change to a self-refresh state, and changing to a self-refresh state based on memory access idle time without explicit notification from a processor regarding the processor power state. Various other embodiments systems, methods, machine readable mediums and apparatuses may provide similar functionality to these exemplary embodiments. ## Claims ### Claim 1 A method for memory to enter self refresh comprising: calculating an amount of memory access idle time; determining if memory access idle time exceeds one of an AC threshold and a DC threshold to change to a self refresh state, wherein the AC threshold corresponds to operation when AC power is provided and the DC threshold corresponds to operation when DC power is provided; and changing to a self refresh state based on memory access idle time without explicit notification from a processor regarding the processor power state. ### Claim 2 (depends on 1) The method of claim 1, wherein the memory access idle time is a minimum duration in a specific power state. ### Claim 3 (depends on 1) The method of claim 1, further comprising demoting to a higher power state if the memory access idle time is less than a threshold. ### Claim 4 (depends on 1) The method of claim 1 wherein the memory access idle time is a duty cycle threshold during an evaluation interval. ### Claim 5 (depends on 1) The method of claim 1 wherein the memory access idle time is evaluated over a sliding window evaluation period using a finite impulse response (FIR) filter. ### Claim 6 (depends on 1) The method of claim 1 wherein the memory access idle time is evaluated over a sliding window evaluation period using an infinite impulse response (IIR) filter. ### Claim 7 An apparatus comprising: a link coupled with a memory; and circuitry coupled with the link, the circuitry to: calculate an amount of memory access idle time over the link; determine if memory access idle time exceeds one of an AC threshold and a DC threshold to change to a self refresh state, wherein the AC threshold corresponds to operation when AC power is provided and the DC threshold corresponds to operation when DC power is provided; and change to a self refresh state based on memory access idle time without explicit notification from a processor regarding the processor power state. ### Claim 8 (depends on 7) The apparatus of claim 7, wherein the memory access idle time is a minimum duration in a specific power state. ### Claim 9 (depends on 7) The apparatus of claim 7, the circuitry further to demote to a higher power state if the memory access idle time is less than a threshold. ### Claim 10 (depends on 7) The apparatus of claim 7 wherein the memory access idle time is a duty cycle threshold during an evaluation interval. ### Claim 11 (depends on 7) The apparatus of claim 7 wherein the memory access idle time is evaluated over a sliding window evaluation period using a finite impulse response (FIR) filter. ### Claim 12 (depends on 7) The apparatus of claim 7 wherein the memory access idle time is evaluated over a sliding window evaluation period using an infinite impulse response (IIR) filter. ### Claim 13 A system comprising: an integrated battery power source to power circuitry; a memory coupled with a link; and circuitry coupled with the link, the circuitry to: calculate an amount of memory access idle time on the link; determine if memory access idle time exceeds one of an AC threshold and a DC threshold to change to a self refresh state, wherein the AC threshold corresponds to operation when AC power is provided and the DC threshold corresponds to operation when DC power is provided; and change to a self refresh state based on memory access idle time without explicit notification from a processor regarding the processor power state. ### Claim 14 (depends on 13) The system of claim 13, wherein the memory access idle time is a minimum duration in a specific power state. ### Claim 15 (depends on 13) The system of claim 13, where the circuitry is further to demote to a higher power. ### Claim 16 (depends on 13) The system of claim 13 wherein the memory access idle time is a duty cycle threshold during an evaluation interval. ### Claim 17 (depends on 13) The system of claim 13 wherein the memory access idle time is evaluated over a sliding window evaluation period using a finite impulse response (FIR) filter. ### Claim 18 (depends on 13) The system of claim 13 wherein the memory access idle time is evaluated over a sliding window evaluation period using an infinite impulse response (IIR) filter.