# US 7,613,912 B2 · System and method for simulating hardware interrupts > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,613,912 B2 - Document ID: US7613912B2 - Status: Granted - Kind: B2 - Application number: 11/771,688 - Filed: 2007-06-29 - Published: 2007-12-13 - Granted: 2009-11-03 - Earliest claimed: 2004-12-02 - Assignees: International Business Machines Corporation - Inventors: David John Erb - Web page: https://patentgrep.com/patent/US7613912B2 ## CPC - G06F 30/33: Design verification, e.g. functional simulation or model checking - G06F 8/445: {Exploiting fine grain parallelism, i.e. parallelism at instruction level (run-time instruction scheduling G06F9/3836)} - G06F 9/30058: {Conditional branch instructions} - G06F 9/323: {for indirect branch instructions} - G06F 9/3836: {Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A system and method is provided to simulate hardware interrupts by inserting instructions into a stream of instructions where a “no operation” (or NOOP) instruction would normally be inserted. The instruction is inserted is a conditional branch instruction, called a BISLED, that branches if there is external data in a known memory area. In one embodiment, the processor has at least two pipelines that need to be aligned so that certain instructions are scheduled for the first pipeline and other instructions are scheduled for the other. In this embodiment, the BISLED also serves the purpose of re-aligning the instruction stream so that instructions are placed in the correct pipeline based upon the function performed by the instruction. ## Claims ### Claim 1 A computer-implemented method comprising: identifying a plurality of unused slots in a plurality of pipelines, wherein each of the pipelines include instructions that are scheduled to execute on a processor, wherein the processor does not have hardware interrupt capabilities; inserting, in a plurality of the identified unused slots, a conditional branch instruction, wherein the conditional branch instruction, when executed, branches on external data; executing the inserted conditional branch instructions, wherein a predetermined memory location is checked each time each of the inserted conditional branch instructions is executed; in response to no data being present in the predetermined memory location, the processor takes no action; and in response to data being present in the predetermined memory location, the processor branches to a registered interrupt handler. ### Claim 2 (depends on 1) The method of claim 1 wherein an instruction stream corresponding to a software program is loaded in the plurality of pipelines, wherein the processor is one of a plurality of heterogeneous processors that share a common memory and a common bus, and wherein the predetermined memory location is included in the shared common memory, the method further comprising: writing, from a different processor included in the plurality of heterogeneous processors, the data to the predetermined memory location. ### Claim 3 (depends on 2) The method of claim 2 further comprising: executing the registered interrupt handler in response to the branching; and reading, by the registered interrupt handler, the data stored in the predetermined memory location. ### Claim 4 (depends on 3) The method of claim 3 further comprising: handling, after the branching, a request from an external program, wherein the external program wrote the data to the predetermined memory location; after handling the request, clearing the predetermined memory location. ### Claim 5 (depends on 4) The method of claim 4 wherein, after clearing the predetermined memory location, the method further comprises: resuming execution of the instruction stream. ### Claim 6 (depends on 1) The method of claim 1 wherein the conditional branch instruction is a Branch Indirect and Set Link if External Data (BISLED) instruction. ### Claim 7 (depends on 1) The method of claim 1 wherein the predetermined memory location is a register. ### Claim 8 A information handling system comprising: a plurality of heterogeneous processors included in a single silicon substrate, wherein a selected one of the processors includes a plurality of pipelines and the selected processor does not have hardware interrupt capabilities; a common memory also included in the single silicon substrate, the common memory accessible by the heterogeneous processors using a common bus; and a software tool that inserts conditional branch instructions in the plurality of pipelines, wherein the software tool, when executed by at least one of the processors, performs steps that include: identifying a plurality of unused slots in the plurality of pipelines, wherein each of the pipelines include instructions that are scheduled to execute on the selected processor; inserting, in a plurality of the identified unused slots, a conditional branch instruction, wherein the conditional branch instruction, when executed, branches on external data; executing the instructions including the inserted conditional branch instructions, wherein a predetermined memory location in the common memory is checked each time each of the inserted conditional branch instructions is executed; in response to no data being present in the predetermined memory location, the selected processor takes no action; and in response to data being present in the predetermined memory location, the selected processor branches to a registered interrupt handler. ### Claim 9 (depends on 8) The information handling system of claim 8 wherein an instruction stream corresponding to a software program is loaded in the plurality of pipeline and the software tool performs a further step comprising: writing, from a different processor included in the plurality of heterogeneous processors, the data to the predetermined memory location. ### Claim 10 (depends on 9) The information handling system of claim 9 wherein the software tool performs further steps comprising: executing the registered interrupt handler in response to the branching; and reading, by the registered interrupt handler, the data stored in the predetermined memory location. ### Claim 11 (depends on 10) The information handling system of claim 10 wherein the software tool performs further steps comprising: handling, after the branching, a request from an external program, wherein the external program wrote the data to the predetermined memory location; after handling the request, clearing the predetermined memory location. ### Claim 12 (depends on 11) The information handling system of claim 11 wherein, after clearing the predetermined memory location, the software tool performs further an additional step comprising: resuming execution of the instruction stream. ### Claim 13 (depends on 8) The information handling system of claim 8 wherein the conditional branch instruction is a Branch Indirect and Set Link if External Data (BISLED) instruction, and wherein the predetermined memory location is a register. ### Claim 14 A computer program product stored on a computer storage media that includes computer instructions that, when executed by an information handling system, causes the information handling system to perform steps comprising: identifying a plurality of unused slots in a plurality of pipelines, wherein each of the pipelines include instructions that are scheduled to execute on a processor, wherein the processor does not have hardware interrupt capabilities; inserting, in a plurality of the identified unused slots, a conditional branch instruction, wherein the conditional branch instruction, when executed, branches on external data; executing the inserted conditional branch instructions, wherein a predetermined memory location is checked each time each of the inserted conditional branch instructions is executed; in response to no data being present in the predetermined memory location, the processor takes no action; and in response to data being present in the predetermined memory location, the processor branches to a registered interrupt handler. ### Claim 15 (depends on 14) The computer program product of claim 14 wherein an instruction stream corresponding to a software program is loaded in the plurality of pipelines, wherein the processor is one of a plurality of heterogeneous processors that share a common memory and a common bus, and wherein the predetermined memory location is included in the shared common memory, and wherein the instructions, when executed, cause the information handling system to perform further steps comprising: writing, from a different processor included in the plurality of heterogeneous processors, the data to the predetermined memory location. ### Claim 16 (depends on 15) The computer program product of claim 15 wherein the instructions, when executed, cause the information handling system to perform further steps comprising: executing the registered interrupt handler in response to the branching; and reading, by the registered interrupt handler, the data stored in the predetermined memory location. ### Claim 17 (depends on 16) The computer program product of claim 16 wherein the instructions, when executed, cause the information handling system to perform further steps comprising: handling, after the branching, a request from an external program, wherein the external program wrote the data to the predetermined memory location; after handling the request, clearing the predetermined memory location. ### Claim 18 (depends on 17) The computer program product of claim 17 wherein, after clearing the predetermined memory location, and wherein the instructions, when executed, cause the information handling system to perform a further step comprising: resuming execution of the instruction stream. ### Claim 19 (depends on 14) The computer program product of claim 14 wherein the conditional branch instruction is a Branch Indirect and Set Link if External Data (BISLED) instruction. ### Claim 20 (depends on 14) The computer program product of claim 14 wherein the predetermined memory location is a register.