# US 7,613,911 B2 · Prefetching exception vectors by early lookup exception vectors within a cache memory > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,613,911 B2 - Document ID: US7613911B2 - Status: Granted - Kind: B2 - Application number: 10/798,890 - Filed: 2004-03-12 - Published: 2005-09-15 - Granted: 2009-11-03 - Earliest claimed: 2004-03-12 - Assignees: Arm Limited - Inventors: Andrew Burdass - Web page: https://patentgrep.com/patent/US7613911B2 ## CPC - G06F 9/3861: {Recovery, e.g. branch miss-prediction, exception handling (error detection or correction G06F11/00)} - G06F 9/3804: {for branches, e.g. hedging, branch folding} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract An integrated circuit processor core 4 is provided with an instruction pipeline 20 along which program instructions advance. When an exception condition occurs part way through execution of a particular program instruction, then a prefetch of the exception handling program instruction corresponding to that exception is initiated before the currently executing program instruction has completed. In this way the exception handling program instruction is more rapidly available to start the exception processing. The early prefetch may involve performing a lookup in a cache memory 6 and any necessary linefill upon a miss. In addition, the exception handling program instruction amy also be fed into the instruction pipeline 20 before an instruction boundary is reached. ## Claims ### Claim 1 Apparatus for processing data, said apparatus comprising: a cache memory operable to store program instructions to be executed; an instruction pipeline including an instruction prefetch unit; and an exception controller, responsive to an exception signal signaling an exception, for triggering exception processing by forcing program execution starting from an exception handling program instruction stored at a predetermined memory location; wherein upon receipt of said exception signal part way through execution of a current program instruction, said exception controller triggering a lookup of said exception handling program instruction within said cache memory and, if said exception handling program instruction is not present within said cache memory, triggering a cache linefill operation to read said exception handing program instruction from a main memory to said cache memory, and, upon completion of execution of said current program instruction, if said exception is still current, then said instruction prefetch unit fetches said exception handling program instruction from said cache memory. ### Claim 2 (depends on 1) Apparatus as claimed in claim 1, wherein execution of said current instruction lasts for a plurality of clock cycles and lookup of said exception handling program instruction within said cache memory starts part way through said plurality of clock cycles. ### Claim 3 (depends on 1) Apparatus as claimed in claim 1, wherein said exception handling program instruction redirects program execution to an exception handling routine. ### Claim 4 (depends on 1) Apparatus as claimed in claim 1, wherein said exception controller is an interrupt controller, said exception signal is an interrupt signal and said exception handling program instruction is and interrupt handling program instruction. ### Claim 5 (depends on 1) Apparatus as claimed in claim 1, wherein said exception is one of a data abort and a prefetch abort. ### Claim 6 (depends on 1) Apparatus as claimed in claim 1, wherein said cache memory and said exception controller are parts of a processor core. ### Claim 7 (depends on 1) Apparatus as claimed in claim 1, wherein said apparatus is an integrated circuit. ### Claim 8 A method of processing data, said method comprising the steps of: storing program instructions to be executed within a cache memory; processing program instructions with an instruction pipeline including an instruction prefetch unit; and triggering, in response to an exception signal, exception processing by forcing program execution starting from an exception handling program instruction stored at a predetermined memory location; wherein, upon receipt of said exception signal part way through execution of a current program instruction, said triggering step includes triggering a lookup of said exception handling program instruction within said cache memory and, if said exception handling program instruction is not present within said cache memory, said triggering step includes triggering a cache linefill operation to read said exception handing program instruction from a main memory to said cache memory, and, upon completion of execution of said current program instruction, if said exception is still current, then said instruction prefetch unit fetches said exception handling program instruction from said cache memory. ### Claim 9 (depends on 8) A method as claimed in claim 8, wherein execution of said current instruction lasts for a plurality of clock cycles and lookup of said exception handling program instruction within said cache memory starts part way through said plurality of clock cycles. ### Claim 10 (depends on 8) A method as claimed in claim 8, wherein said exception handling program instruction redirects program execution to an exception handling routine. ### Claim 11 (depends on 8) A method as claimed in claim 8, wherein said exception signal is an interrupt signal and said exception handling program instruction is and interrupt handling program instruction. ### Claim 12 (depends on 8) A method as claimed in claim 8, wherein said exception is one of a data abort and a prefetch abort. ### Claim 13 (depends on 8) A method as claimed in claim 8, wherein said method is performed within a processor core. ### Claim 14 (depends on 8) A method as claimed in claim 8, wherein method is performed within an integrated circuit.