# US 7,613,909 B2 · Resuming thread to service ready port transferring data externally at different clock rate than internal circuitry of a processor > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,613,909 B2 - Document ID: US7613909B2 - Status: Granted - Kind: B2 - Application number: 11/785,345 - Filed: 2007-04-17 - Published: 2008-10-23 - Granted: 2009-11-03 - Earliest claimed: 2007-04-17 - Assignees: Xmos Ltd - Inventors: Michael David May; Peter Hedinger; Alastair Dixon - Web page: https://patentgrep.com/patent/US7613909B2 ## CPC - G06F 13/385: {for adaptation of a particular data processing system to different peripheral devices} - G06F 9/30032: {Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE} - G06F 9/3009: {Thread control instructions} - G06F 9/3851: {from multiple instruction streams, e.g. multistreaming} - G06F 13/4059: {where the synchronisation uses buffers, e.g. for speed matching between buses} - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract A processor has an interface portion and an internal environment. The interface portion comprises at least one port. The internal environment comprises an execution unit arranged to execute instructions in dependence on a first timing signal and to transfer data between the interior portion and the at least one port in dependence on the first timing signal; and a thread scheduler for scheduling a plurality of threads for execution by the execution unit, each thread comprising a sequence of instructions and the thread scheduler being arranged to schedule the threads in dependence on the first timing signal. The port is arranged to transfer data between the port and an external environment in dependence on a second timing signal, and to alter a ready signal in dependence on the second timing signal to indicate a transfer of data with the external environment. The thread scheduler is configured to schedule one or more associated threads for execution in dependence on the ready signal. ## Claims ### Claim 1 A processor having interface circuitry and internal circuitry, the interface circuitry comprising at least one port and the internal circuitry comprising: an execution unit arranged to execute instructions in dependence on a first timing signal and to transfer data between the internal circuitry and the at least one port in dependence on the first timing signal; and a thread scheduler for scheduling a plurality of threads for execution by the execution unit, each thread comprising a sequence of instructions and the thread scheduler being arranged to schedule the threads in dependence on the first timing signal; wherein the at least one port is arranged to transfer data between the port and circuitry external to the processor in dependence on a second timing signal, and to alter a ready signal in dependence on said second timing signal to indicate a transfer of data with the external circuitry; and the thread scheduler is configured such that said scheduling comprises: starting execution of one or more threads each including one of an input instruction and an output instruction which when executed performs a transfer of data between the at least one port and the internal circuitry, then suspending execution of said one or more threads, and then continuing execution of said one or more threads in dependence on the ready signal. ### Claim 2 (depends on 1) A processor according to claim 1, wherein the interface circuitry comprises a plurality of ports arranged to simultaneously transfer data between each port and the external circuitry in dependence on the second timing signal; each port is adapted to alter a respective ready signal in dependence on said second timing signal to indicate the transfer with the external environment, said continuation by the thread scheduler being in dependence on the ready signals; and the execution unit is arranged to transfer data between the internal circuitry and each of the ports at different times in dependence on the first timing signal. ### Claim 3 (depends on 1) A processor according to claim 1, wherein the transfer between port and external circuitry comprises an input operation whereby data is captured into said at least one port from the external circuitry, and said alteration comprises setting said ready signal into a first state which indicates the availability of that data for input to the internal circuitry. ### Claim 4 (depends on 1) A processor according to claim 1, wherein the transfer between port and external circuitry comprises an output operation whereby data is presented from each of said at least one ports to the external circuitry, and said alteration comprises setting said ready signal into a second state which indicates the availability of the at least one port for further transfer of data with the external circuitry. ### Claim 5 (depends on 3) A processor according to claim 3, wherein the execution unit is adapted to execute an input instruction which inputs data from a port to the internal environment provided that the ready signal is in the first state, the input instruction being included in said one or more threads. ### Claim 6 (depends on 4) A processor according to claim 4, wherein the execution unit is adapted to execute an output instruction which outputs data from the internal environment to a port provided that the ready signal is in the second state, the output instruction being included in said one or more threads. ### Claim 7 (depends on 5) A processor according to claim 5, wherein the execution unit is adapted to set said respective ready signal into the second state upon completion of the input instruction. ### Claim 8 (depends on 6) A processor according to claim 6, wherein the execution unit is adapted to set said respective ready signal into the first state upon completion of the output instruction. ### Claim 9 (depends on 5) A processor according to claim 5, wherein said scheduling by the thread scheduler comprises suspending execution of the input instruction's thread until the respective ready signal is set to said first state. ### Claim 10 (depends on 6) A processor according to claim 6, wherein said scheduling by the thread scheduler comprises suspending execution of the output instruction's thread until the respective ready signal is set to said second state. ### Claim 11 (depends on 1) A processor according to claim 1, wherein: the transfer between port and external circuitry comprises an input operation whereby data is captured into said at least one port from the external circuitry, and said alteration comprises setting said ready signal into a first state which indicates the availability of that data for input to the internal circuitry; the transfer between port and external circuitry further comprises an output operation whereby data is presented from each of said at least one ports to the external circuitry, and said alteration comprises setting said ready signal into a second state which indicates the availability of the at least one port for further transfer of data with the external circuitry, the execution unit is adapted to execute an input instruction which inputs data from a port to the internal environment provided that the ready signal is in the first state, the input instruction being included in said one or more threads; the execution unit is adapted to execute an output instruction which outputs data from the internal environment to a port provided that the ready signal is in the second state, the output instruction being included in said one or more threads; the execution unit is adapted to set said respective ready signal into the second state upon completion of the input instruction; the execution unit is adapted to set said respective ready signal into the first state upon completion of the output instruction. ### Claim 12 (depends on 1) A processor according to claim 1, wherein: the transfer between port and external circuitry comprises an input operation whereby data is captured into said at least one port from the external circuitry, and said alteration comprises setting said ready signal into a first state which indicates the availability of that data for input to the internal circuitry, the transfer between port and external circuitry further comprises an output operation whereby data is presented from each of said at least one ports to the external circuitry, and said alteration comprises setting said ready signal into a second state which indicates the availability of the at least one port for further transfer of data with the external circuitry; and the second timing signal comprises a sequence of alternating primary and secondary edges, and the second timing signal is arranged to trigger the input operation on a primary edge and the output operation on a secondary edge. ### Claim 13 (depends on 12) A processor according to claim 12, wherein said setting of the ready signal into the first state is performed on said primary edge, and said setting of the ready signal into the second state is performed on said secondary edge. ### Claim 14 (depends on 12) A processor according to claim 12, wherein the execution unit is configured to execute a rising mode instruction which sets one of said at least one ports to a rising mode in which said primary edge is a rising edge and said secondary edge is a falling edge, and a falling mode instruction which sets one of said at least one ports to a falling mode in which said primary edge is a falling edge and said secondary edge is a rising edge. ### Claim 15 (depends on 1) A processor according to claim 1, wherein the thread scheduler is configured to maintain a set of runnable threads, and said scheduling by the thread scheduler comprises scheduling threads from said set in dependence on the first timing signal and suspending a thread by removing it from said set. ### Claim 16 (depends on 1) A processor according to claim 1, wherein said external circuitry comprises at least one pin of an integrated circuit in which said processor is housed. ### Claim 17 (depends on 1) A processor according to claim 1, wherein said external circuitry comprises another processor on an integrated circuit in which said processor is housed. ### Claim 18 (depends on 1) A processor according to claim 1, wherein the transfer of data between a port and the internal circuitry comprises a transfer between that port and the execution unit. ### Claim 19 (depends on 1) A processor according to claim 1, wherein the internal circuitry comprises a bus and the transfer of data between a port and the internal circuitry comprises a transfer between that port and the bus. ### Claim 20 (depends on 1) A processor according to claim 1, wherein the internal circuitry comprises a plurality of sets of registers, each set storing information relating to a respective one of said plurality of threads, and the transfer between a port and the internal circuitry comprises a transfer between that port and one of said registers. ### Claim 21 (depends on 1) A processor according to claim 1, wherein at least one of the first and second timing signals is a clock signal. ### Claim 22 (depends on 1) A processor according to claim 1, wherein at least one of the first and second timing signals is an irregular timing signal. ### Claim 23 (depends on 1) A processor according to claim 1, wherein the interface portion comprises a timing signal generator operable to derive the second timing signal from an external timing signal. ### Claim 24 (depends on 1) A processor according to claim 1, wherein interface portion comprises a timing signal generator operable to produce the second timing signal by dividing a frequency of the first timing signal by a factor. ### Claim 25 (depends on 1) A processor according to claim 1, wherein the interface portion comprises a register associated with the at least one port for storing an identifier of a timing signal generator, and a switch box operable to supply the second timing signal from the identified timing signal generator to the port; and the execution unit is configured to execute a set generator instruction to store the identifier. ### Claim 26 (depends on 24) A processor according to claim 24, wherein the execution unit is configured to execute a set factor instruction to allocate said factor. ### Claim 27 (depends on 1) A processor according to claim 1, wherein the at least one port has a data mode in which it transfers data and a timing output mode in which it outputs the second timing signal. ### Claim 28 (depends on 1) A processor according to claim 1, wherein the interface circuitry comprises a plurality of ports and the internal circuitry comprises at least one register, the register being arranged to store data input from a first one of said ports; and the execution unit is arranged to execute a shift instruction to shift the data in the register by the width of the first port, and to subsequently execute one of said input instructions to input data from a second one of said ports into the register, thereby concatenating the data from the first and second ports. ### Claim 29 (depends on 1) A processor according to claim 1, wherein the interface circuitry comprises a plurality of ports each arranged to transfer data between the port and the external circuitry in dependence on a respective second timing signal, each respective second timing signal being derived from a different external source. ### Claim 30 A method of scheduling threads in a processor having interface circuitry and internal circuitry, the interface circuitry comprising at least one port and the internal circuitry comprising an execution unit and a thread scheduler, the method comprising: operating the execution unit to execute instructions in dependence on a first timing signal and to transfer data between the internal circuitry and the at least one port in dependence on the first timing signal; operating the thread scheduler to schedule a plurality of threads for execution by the execution unit, each thread comprising a sequence of instructions and the scheduling being in dependence on the first timing signal; transferring data between the at least one port and circuitry external to the processor in dependence on a second timing signal; and altering a ready signal in dependence on said second timing signal to indicate a transfer of data with the external circuitry; wherein said scheduling comprises: starting execution of one or more threads each including one of an input instruction and an output instruction which when executed performs a transfer of data between the at least one port and the interior external circuitry, then suspending execution of said one or more threads, and then continuing execution of said one or more threads in dependence on the ready signal. ### Claim 31 (depends on 30) A method according to claim 30, wherein the interface circuitry comprises a plurality of ports, and the method comprises: simultaneously transferring data between each port and the external circuitry in dependence on the second timing signal; altering a respective ready signal for each port in dependence on said second timing signal to indicate the transfer with the external circuitry, said continuation being in dependence on the ready signals; and operating the execution unit to transfer data between the internal circuitry and each of the ports at different times in dependence on the first timing signal. ### Claim 32 (depends on 30) A method according to claim 30, wherein the transfer between port and external circuitry comprises an input operation whereby data is captured into said at least one port from the external circuitry, and said alteration comprises setting said ready signal into a first state which indicates the availability of that data for input to the internal circuitry. ### Claim 33 (depends on 30) A method according claim 30, wherein the transfer between port and external circuitry comprises an output operation whereby data is presented from each of said at least one ports to the external circuitry, and said alteration comprises setting said ready signal into a second state which indicates the availability of the at least one port for further transfer of data with the internal circuitry. ### Claim 34 (depends on 32) A method according to claim 32, comprising operating the execution unit to execute an input instruction which inputs data from a port to the internal environment provided that said ready signal is in the first state, the input instruction being included in said one or more threads. ### Claim 35 (depends on 33) A method according to claim 33, comprising operating the execution unit to execute an output instruction which outputs data from the internal environment to a port provided that said ready signal is in the second state, the output instruction being included in said one or more threads. ### Claim 36 (depends on 34) A method according to claim 34, comprising setting said respective ready signal into the second state upon completion of the input instruction. ### Claim 37 (depends on 35) A method according to claim 35, comprising setting said respective ready signal into the first state upon completion of the output instruction. ### Claim 38 (depends on 34) A method according to claim 34, wherein said scheduling comprises suspending execution of the input instruction's thread until the respective ready signal is set to said first state. ### Claim 39 (depends on 35) A method according to claim 35, wherein said scheduling comprises suspending execution of the output instruction's thread until the respective ready signal is set to said second state. ### Claim 40 (depends on 30) A method according to claim 30, wherein: the transfer between port and external circuitry comprises an input operation whereby data is captured into said at least one port from the external circuitry, and said alteration comprises setting said ready signal into a first state which indicates the availability of that data for input to the internal circuitry: the transfer between port and external circuitry further comprises an output operation whereby data is presented from each of said at least one ports to the external circuitry, and said alteration comprises setting said ready signal into a second state which indicates the availability of the at least one port for further transfer of data with the internal circuitry; the method comprises operating the execution unit to execute an input instruction which inputs data from a port to the internal environment provided that said ready signal is in the first state, the input instruction being included in said one or more threads; the method comprises operating the execution unit to execute an output instruction which outputs data from the internal environment to a port provided that said ready signal is in the second state, the output instruction being included in said one or more threads; the method comprises setting said respective ready signal into the second state upon completion of the input instruction; and the method comprises setting said respective ready signal into the first state upon completion of the output instruction. ### Claim 41 (depends on 30) A method according to claim 30, wherein the transfer between port and external circuitry comprises an input operation whereby data is captured into said at least one port from the external circuitry, and said alteration comprises setting said ready signal into a first state which indicates the availability of that data for input to the internal circuitry; the transfer between port and external circuitry further comprises an output operation whereby data is presented from each of said at least one ports to the external circuitry, and said alteration comprises setting said ready signal into a second state which indicates the availability of the at least one port for further transfer of data with the internal circuitry; and the second timing signal comprises a sequence of alternating primary and secondary edges, and the method comprises triggering the input operation on a primary edge and the output operation on a secondary edge. ### Claim 42 (depends on 41) A method according to claim 41, wherein said setting of the ready signal into the first state is performed on said primary edge, and said setting of the ready signal into the second state is performed on said secondary edge. ### Claim 43 (depends on 41) A method according to claim 41, comprising operating the execution unit to execute a rising mode instruction which sets one of said at least one ports to a rising mode in which said primary edge is a rising edge and said secondary edge is a falling edge, and a falling mode instruction which sets one of said at least one ports to a falling mode in which said primary edge is a falling edge and said secondary edge is a rising edge. ### Claim 44 (depends on 30) A method according to claim 30, comprising operating the thread scheduler to maintain a set of runnable threads, wherein said scheduling comprises scheduling threads from said set in dependence on the first timing signal and suspending a thread by removing it from said set. ### Claim 45 (depends on 30) A method according to claim 30, wherein said external circuitry comprises at least one pin of an integrated circuit in which said processor is housed. ### Claim 46 (depends on 30) A method according to claim 30, wherein said external circuitry comprises another processor on an integrated circuit in which said processor is housed. ### Claim 47 (depends on 30) A processor according to claim 30, wherein the transfer of data between a port and the internal circuitry comprises a transfer between that port and the execution unit. ### Claim 48 (depends on 30) A method according to claim 30, wherein the internal circuitry comprises a bus and the transfer of data between a port and the internal circuitry comprises a transfer between that port and the bus. ### Claim 49 (depends on 30) A method according to claim 30, wherein the internal circuitry comprises a plurality of sets of registers, each set storing information relating to a respective one of said plurality of threads, and the transfer between a port and the internal circuitry comprises a transfer between that port and one of said registers. ### Claim 50 (depends on 30) A method according to claim 30, wherein at least one of the first and second timing signals is a clock signal. ### Claim 51 (depends on 30) A method according to claim 30, wherein at least one of the first and second timing signals is an irregular timing signal. ### Claim 52 (depends on 30) A method according to claim 30, comprising deriving the second timing signal from an external timing signal. ### Claim 53 (depends on 30) A method according to claim 30, comprising producing the second timing signal by dividing a frequency of the first timing signal by a factor. ### Claim 54 (depends on 30) A method according to claim 30, comprising operating the execution unit to execute a set generator instruction to store an identifier of a timing signal generator in a register associated with the at least one port, and supplying the second timing signal from the identified timing signal generator to the port. ### Claim 55 (depends on 53) A method according to claim 53, comprising operating the execution unit to execute a set factor instruction to allocate said factor. ### Claim 56 (depends on 30) A method according to claim 30, comprising setting the at least one port to a data mode in which it transfers data, and setting the at least one port to a clock output mode in which it outputs the second clock signal. ### Claim 57 (depends on 30) A method according to claim 30, wherein the interface circuitry comprises a plurality of ports and the internal circuitry comprises at least one register, the register being arranged to store data input from a first one of said ports; the method comprising operating the execution unit to execute a shift instruction to shift the data in the register by the width of the first port, and to subsequently execute one of said input instructions to input data from a second one of said ports into the register, thereby concatenating the data from the first and second ports. ### Claim 58 (depends on 30) A method according to claim 30, wherein the interface circuitry comprises a plurality of ports, the method comprising transferring data between each port and the external circuitry in dependence on a respective second timing signal, each respective second timing signal being derived from a different external source. ### Claim 59 A mobile terminal having a mobile applications processor, at least one peripheral device, and an interface processor connected between the mobile applications processor and the peripheral device, the interface processor having interface circuitry and internal circuitry, the interface circuitry comprising at least one port and the internal circuitry comprising: an execution unit arranged to execute instructions in dependence on a first timing signal and to transfer data between the internal circuitry and the at least one port in dependence on the first timing signal; and a thread scheduler for scheduling a plurality of threads for execution by the execution unit, each thread comprising a sequence of instructions and the thread scheduler being arranged to schedule the threads in dependence on the first timing signal; wherein the at least one port is arranged to transfer data between the port and the mobile applications processor or peripheral device in dependence on a second timing signal, and to alter a ready signal in dependence on said second timing signal to indicate a transfer of data with the mobile applications processor or peripheral device; and the thread scheduler is configured such that said scheduling comprises: starting execution of one or more threads each including one of an input instruction and an output instruction which when executed performs a transfer of data between the at least one port and the internal circuitry, then suspending execution of said one or more threads, and then continuing execution of said one or more threads in dependence on the ready signal. ### Claim 60 An array of interconnected processors, at least one of said processors having interface circuitry and internal circuitry, the interface circuitry comprising at least one port and the internal circuitry comprising: an execution unit arranged to execute instructions in dependence on a first timing signal and to transfer data between the internal circuitry and the at least one port in dependence on the first timing signal; and a thread scheduler for scheduling a plurality of threads for execution by the execution unit, each thread comprising a sequence of instructions and the thread scheduler being arranged to schedule the threads in dependence on the first timing signal; wherein the at least one port is arranged to transfer data between the port and another processor in the array in dependence on a second timing signal, and to alter a ready signal in dependence on said second timing signal to indicate a transfer of data with said other processor of the array; and the thread scheduler is configured such that said scheduling comprises: starting execution of said one or more threads each including one of an input instruction and an output instruction which when executed performs a transfer of data between the at least one port and the internal circuitry, then suspending execution of said one or more threads, and then continuing execution of said one or more threads in dependence on the ready signal. ### Claim 61 A processor having an interface means and internal circuitry, the interface means comprising port means and the internal circuitry comprising: execution means for executing instructions in dependence on a first timing signal and for transferring data between the internal circuitry and the port means in dependence on the first timing signal; and thread scheduling means for scheduling a plurality of threads for execution by the execution means, each thread comprising a sequence of instructions and the scheduling by the thread scheduling means being in dependence on the first timing signal; wherein the port means are for transferring data between the port means and circuitry external to the processor in dependence on a second timing signal, and for altering a ready signal in dependence on said second timing signal to indicate a transfer of data with the external circuitry; and the thread scheduling means is for scheduling by: starting execution of one or more threads each including one of an input instruction and an output instruction which when executed performs a transfer of data between the port means and the internal circuitry, then suspending execution of said one or more threads, and then continuing execution of said one or more threads in dependence on the ready signal. ### Claim 62 A computer program product for scheduling threads in a processor having interface circuitry and internal circuitry, the interface circuitry comprising at least one port and the internal circuitry comprising an execution unit and a thread scheduler, comprising a storage media and a computer executable program wherein the program comprising code which when executed by a computer performs the steps of: transferring data between the internal circuitry and the at least one port in dependence on the first timing signal; operating the thread scheduler to schedule a plurality of threads for execution by the execution unit, each thread comprising a sequence of instructions and the scheduling being in dependence on the first timing signal; transferring data between the at least one port and circuitry external to the processor in dependence on a second timing signal; and altering a ready signal in dependence on said second timing signal to indicate a transfer of data with the external circuitry; wherein said scheduling comprises: starting execution of one or more threads each including one of an input instruction and an output instruction which when executed performs a transfer of data between the at least one port and the internal circuitry, then suspending execution of said one or more threads, and then continuing execution of said one or more threads in dependence on the ready signal.