# US 7,613,901 B2 · Comparators in IC with programmably controlled positive / negative hysteresis level and open-drain / push-pull output coupled to crossbar switch or rising / falling edge interrupt generation

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- Number: US 7,613,901 B2
- Document ID: US7613901B2
- Status: Granted
- Kind: B2
- Application number: 11/694,629
- Filed: 2007-03-30
- Published: 2007-12-27
- Granted: 2009-11-03
- Earliest claimed: 2000-06-19
- Assignees: Silicon Labs CP, Inc.
- Inventors: Donald E. Alfano; Danny J. Allred; Douglas S. Piasecki; Kenneth W. Fernald; Ka Y. Leung; Brian Caloway; Alvin Storvik; Paul Highley; Douglas R. Holberg
- Web page: https://patentgrep.com/patent/US7613901B2

## CPC

- G06F 13/385: {for adaptation of a particular data processing system to different peripheral devices}
- G06F 1/08: Clock generators with changeable or programmable clock frequency
- G06F 15/7814: {Specially adapted for real time processing, e.g. comprising hardware timers}
- H03M 1/122: {Shared using a single converter or a part thereof for multiple channels, e.g. a residue amplifier for multiple stages}
- H03M 1/183: {the feedback signal controlling the gain of an amplifier or attenuator preceding the analogue/digital converter}
- H03M 1/462: {Details of the control circuitry, e.g. of the successive approximation register}
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

An integrated circuit package includes a processing core for operating on a set of instructions to carry out predefined processes. A plurality of comparators perform compare operations within the integrated circuit package. At least one control register is associated with each of the plurality of comparators, and each of the plurality of comparators are software programmable to control a hysteresis of the comparators responsive to control bits established in the at least one control register of the comparator by the processing core. An amount of positive hysteresis is programmed via a first group of the control bits and an amount of negative hysteresis is programmed via a second group of the control bits.

## Claims

### Claim 1

An integrated circuit package on a single chip, comprising:
a processing core for operating on a set of instructions to carry out predefined processes;
a plurality of comparators for performing compare operations within the integrated circuit package;
at least one control register associated with each of the plurality of comparators for storing a first group of control bits controlling an amount of positive hysteresis of each of the plurality of comparators and a second group of control bits controlling an amount of negative hysteresis of each of the plurality of comparators;
wherein each of the plurality of comparators are software programmable to control a hysteresis of the plurality of comparators responsive to control bits established in the at least one control register by the processing core, the amount of positive hysteresis programmed via the first group of the control bits in the at least one control register and the amount of negative hysteresis programmed via the second group of the control bits in the at least one control register;
a crossbar switch for assigning an output of the plurality of comparators to package pins; and
wherein when a comparator output is assigned to the package pins, the comparator output can be programmed by the processing core to operate in either an open drain mode or a push-pull mode.

### Claim 2 (depends on 1)

The integrated circuit package of claim 1, wherein positive and negative going symmetry of hysteresis around a threshold voltage may be software programmed responsive to hysteresis symmetry control bits within the at least one control register set by the processing core.

### Claim 3 (depends on 1)

The integrated circuit package of claim 1, wherein each of the plurality of comparators can be enabled or disabled by the processing core responsive to a software programmed bit in the control register.

### Claim 4 (depends on 1)

The integrated circuit package of claim 1, wherein each of the plurality of comparators may be placed in a low power shut down mode by the processing core.

### Claim 5 (depends on 1)

The integrated circuit package of claim 1, wherein each of the plurality of comparators may be software programmed to generate an interrupt on a rising clock edge responsive to a first control bit, a falling clock responsive to a second control bit, and both a rising and falling clock edge responsive to the first and the second control bits.

### Claim 6 (depends on 1)

The integrated circuit package of claim 1, wherein the at least one control register programs each of the plurality of comparators to operate in either an open drain mode or a push-pull mode.

### Claim 7

An integrated circuit package, comprising:
a processing core for operating on a set of instructions to carry out predefined processes;
a plurality of comparators for performing compare operations within the integrated circuit package;
at least one control register associated with each of the plurality of comparators for storing a first group of control bits controlling an amount of positive hysteresis of each of the plurality of comparators and a second group of control bits controlling an amount of negative hysteresis of each of the plurality of comparators; and
wherein each of the plurality of comparators are software programmable to control a hysteresis of the plurality of comparators responsive to control bits established in the at least one control register of the comparator by the processing core, the amount of positive hysteresis programmed via the first group of the control bits in the at least one control register and the amount of negative hysteresis programmed via the second group of the control bits in the at least one control register;
wherein each of the plurality of comparators may be software programmed to generate an interrupt on a rising clock edge responsive to a first control bit, a falling clock responsive to a second control bit, and both a rising and falling clock edge responsive to the first and the second control bits; and
wherein each of the plurality of comparators can be enabled or disabled by the processing core responsive to a software programmed bit in the control register.

### Claim 8 (depends on 7)

The integrated circuit package of claim 7, further including:
a crossbar switch for assigning an output of the plurality of comparators to package pins; and
wherein when a comparator output is assigned to the package pins, the comparator output can be programmed by the processing core to operate in either an open drain mode or a push-pull mode.

### Claim 9 (depends on 7)

The integrated circuit package of claim 7, wherein each of the plurality of comparators may be placed in a low power shut down mode by the processing core.

### Claim 10 (depends on 7)

The integrated circuit package of claim 7, wherein the at least one control register programs each of the plurality of comparators to operate in either an open drain mode or a push-pull mode.

### Claim 11

An integrated circuit package on a single chip, comprising:
a processing core for operating on a set of instructions to carry out predefined processes;
a plurality of comparators for performing compare operations within the integrated circuit package;
at least one control register associated with each of the plurality of comparators for storing a first group of control bits controlling an amount of positive hysteresis of each of the plurality of comparators and a second group of control bits controlling an amount of negative hysteresis of comparators;
wherein each of the plurality of comparators are software programmable to control an amount of hysteresis voltage of each of the plurality of comparators and to control a positive going and negative going symmetry of hysteresis around the amount of hysteresis voltage;
a crossbar switch for assigning an output of the plurality of comparators to package pins; and
wherein when a comparator output is assigned to the package pins, the comparator output can be programmed by the processing core to operate in either an open drain mode or a push-pull mode.