# US 7,613,870 B2 · Efficient memory usage in systems including volatile and high-density memories > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,613,870 B2 - Document ID: US7613870B2 - Status: Granted - Kind: B2 - Application number: 10/992,443 - Filed: 2004-11-18 - Published: 2006-05-18 - Granted: 2009-11-03 - Earliest claimed: 2004-11-18 - Assignees: International Business Machines Corporation - Inventors: Gerald K. Bartley; John M. Borkenhagen; William H. Cochran; William P. Hovis; Paul W. Rudrud - Web page: https://patentgrep.com/patent/US7613870B2 ## CPC - G06F 12/08: in hierarchically structured memory systems, e.g. virtual memory systems - G06F 12/0866: for peripheral storage systems, e.g. disk cache - G06F 2212/205: Hybrid memory, e.g. using both volatile and non-volatile memory - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract A first method for efficient memory usage includes (1) determining whether data retrieved from a first storage device is characterized as data that is primarily read; and (2) if data retrieved from the first storage device is characterized as data that is primarily read (a) writing the retrieved data in a temporary storage device with short write latency; and (b) writing the retrieved data in a high-density memory. Numerous other aspects are provided. ## Claims ### Claim 1 A method for efficient memory usage, comprising: determining whether data retrieved from a first storage device is characterized as data that is primarily read, wherein determining whether data retrieved from the first storage device is characterized as data that is primarily read includes: monitoring for at least one of a processor access pattern to a memory, an attribute associated with a command and a memory address of the command; and identifying data retrieved from the first storage device as characterized as data that is primarily read based on the monitoring; if data retrieved from the first storage device is characterized as data that is primarily read: writing the retrieved data in a temporary storage device with short write latency; and writing the retrieved data in a high-density memory; receiving a request to write data to a memory address in the high-density memory; allocating one or more memory addresses of the temporary storage device equal to a minimum block size that may be written to the high-density memory; writing the data to a memory address in the one or more allocated memory addresses; reading data from memory addresses, which will remain unmodified, included in the block of the high-density memory to which data is to be written; storing data read from the unmodified memory addresses included in the block of the high-density memory to which data is to be written in the one or more allocated memory addresses of the temporary storage device; and writing data stored in the one or more allocated memory addresses of the temporary storage device to the high-density memory. ### Claim 2 (depends on 1) The method of claim 1 further comprising writing the retrieved data into a volatile memory if the data retrieved from the first storage device is not characterized as data that is primarily read. ### Claim 3 (depends on 1) The method of claim 1 further comprising reading the retrieved data from the temporary storage device while writing the retrieved data in the high-density memory. ### Claim 4 (depends on 1) The method of claim 1, wherein monitoring for at least one of a processor access pattern to a memory, an attribute associated with a command and a memory address of the command includes monitoring for at least one of a processor access pattern to a memory, an attribute associated with a command and a memory address of the command, via software. ### Claim 5 (depends on 1) The method of claim 1 wherein monitoring for at least one of a processor access pattern to a memory, an attribute associated with a command and a memory address of the command includes monitoring for at least one of a processor access pattern to a memory, an attribute associated with a command and a memory address of the command, via digital logic. ### Claim 6 (depends on 1) The method of claim 1 wherein the temporary storage device is a cache memory. ### Claim 7 (depends on 6) The method of claim 6 wherein a memory controller includes the cache memory. ### Claim 8 (depends on 1) The method of claim 1 wherein the temporary storage device is a portion of a volatile memory. ### Claim 9 (depends on 1) The method of claim 1 further comprising making memory addresses of the temporary storage device in which the retrieved data is stored available for storing other data. ### Claim 10 (depends on 1) The method of claim 1 further comprising: receiving a request to retrieve data from the first storage device; and retrieving the data from the first storage device. ### Claim 11 (depends on 1) The method of claim 1 further comprising making the one or more allocated memory addresses of the temporary storage device available for storing other data. ### Claim 12 An apparatus for efficient memory usage, comprising: a high-density memory; a volatile memory; a first storage device; a temporary storage device with short write latency; and a monitoring device, coupled to the high-density memory, volatile memory, first storage device, temporary storage device, and adapted to identify data which is characterized as primarily read; wherein the apparatus is adapted to: determine whether data retrieved from the first storage device is characterized as data that is primarily read; and if data retrieved from the first storage device is characterized as data that is primarily read: write the retrieved data in the temporary storage device; and write the retrieved data in the high-density memory, wherein the apparatus is further adapted to: monitor for at least one of a processor access pattern to a memory, an attribute associated with a command and a memory address of the command; identify data retrieved from the first storage device as characterized as data that is primarily read based on the monitoring; receive a request to write data to a memory address in the high-density memory; allocate one or more memory addresses of the temporary storage device equal to a minimum block size that may be written to the high-density memory; write the data to a memory address in the one or more allocated memory addresses; read data from memory addresses, which will remain unmodified, included in the block of the high-density memory to which data is to be written; store data read from the unmodified memory addresses included in the block of the high-density memory to which data is to be written in the one or more allocated memory addresses of the temporary storage device; and write data stored in the one or more allocated memory addresses of the temporary storage device to the high-density memory. ### Claim 13 (depends on 12) The apparatus of claim 12 wherein the apparatus is further adapted to write the retrieved data into the volatile memory if the data retrieved from the first storage device is not characterized as data that is primarily read. ### Claim 14 (depends on 12) The apparatus of claim 12 wherein the apparatus is further adapted to read the retrieved data from the temporary storage device while writing the retrieved data in the high-density memory. ### Claim 15 (depends on 12) The apparatus of claim 12 wherein the apparatus is further adapted to monitor for at least one of a processor access pattern to a memory, an attribute associated with a command and a memory address of the command, via software. ### Claim 16 (depends on 12) The apparatus of claim 12 wherein the apparatus is further adapted to monitor for at least one of a processor access pattern to a memory, an attribute associated with a command and a memory address of the command, via the monitoring device. ### Claim 17 (depends on 12) The apparatus of claim 12 wherein the temporary storage device is a cache memory. ### Claim 18 (depends on 17) The apparatus of claim 17 further comprising a memory controller coupled to the high-density memory, volatile memory and first storage device; and wherein the memory controller includes the cache memory. ### Claim 19 (depends on 12) The apparatus of claim 12 wherein the temporary storage device is a portion of the volatile memory. ### Claim 20 (depends on 12) The apparatus of claim 12 wherein the apparatus is further adapted to make memory addresses of the temporary storage device in which the retrieved data is stored available for storing other data. ### Claim 21 (depends on 12) The apparatus of claim 12 wherein the apparatus is further adapted to: receive a request to retrieve data from the first storage device; and retrieve the data from the first storage device. ### Claim 22 (depends on 12) The apparatus of claim 12 wherein the apparatus is further adapted to make the one or more allocated memory addresses of the temporary storage device available for storing other data.