# US 7,613,858 B1 · Implementing signal processing cores as application specific processors > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,613,858 B1 - Document ID: US7613858B1 - Status: Granted - Kind: B1 - Application number: 11/042,887 - Filed: 2005-01-24 - Granted: 2009-11-03 - Earliest claimed: 2005-01-24 - Assignees: Altera Corporation - Inventors: Robert Jackson; Sambuddhi Hettiaratchi - Web page: https://patentgrep.com/patent/US7613858B1 ## CPC - G06F 30/30: Circuit design - G06F 17/142: {Fast Fourier transforms, e.g. using a Cooley-Tukey type algorithm} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Methods and apparatus are provided for efficiently implementing signal processing cores as application specific processors. A signal processing core, such as a Fast Fourier Transform (FFT) core or a Finite Impulse Response (FIR) core includes a data path and a control path. A control path is implemented using processor components to increase resource efficiency. Both the data path and the control path can be implemented using function units that are selected, parameterized, and interconnected. A variety of signal processing algorithms can be implemented on the same application specific processor. ## Claims ### Claim 1 A method for implementing a custom processor, the method comprising: receiving a plurality of function units corresponding to components for implementing a signal processing core as an application specific processor, the signal processing core including a Fast Fourier Transform (FFT) data path, wherein the plurality of function units for implementing the signal processing core are selected and parameterized by a user, wherein a defined function unit from a library that approximates an undefined function unit is selected when the plurality of function units includes the undefined function unit; receiving interconnection information for connecting the plurality of function units; and generating a hardware description for instantiating the plurality of function units and connecting the plurality of function units. ### Claim 2 (depends on 1) The method of claim 1, wherein the plurality of function units comprises a loadable shifter, a loadable adder/subtractor, and a loadable counter. ### Claim 3 (depends on 2) The method of claim 2, wherein the plurality of function units further comprises a register file and a registered 3:1 multiplexer. ### Claim 4 (depends on 1) The method of claim 1, wherein Fast Fourier Transform (FFT) arguments are swapped after FFT real portion data is read from memory but before the FFT real portion data is written to cache. ### Claim 5 (depends on 1) The method of claim 1, wherein the plurality of function units includes a plurality of defined function units. ### Claim 6 (depends on 1) The method of claim 1, wherein the signal processing core is a Fast Fourier Transform (FFT) core. ### Claim 7 (depends on 6) The method of claim 6, wherein the FFT core supports Radix-2 and Radix-4 modes. ### Claim 8 (depends on 7) The method of claim 7, wherein the signal processing core is reprogrammable as a Finite Impulse Response (FIR) core. ### Claim 9 (depends on 1) The method of claim 1, wherein the signal processing core is reprogrammable as a Fast Fourier Transform (FFT) core. ### Claim 10 (depends on 5) The method of claim 5, wherein the plurality of defined function units are defined by the user or a function unit library. ### Claim 11 (depends on 10) The method of claim 10, wherein the function unit library includes function units such as registers, memory, counters, multiply accumulate blocks, input channels, output channels, and shifters. ### Claim 12 (depends on 1) The method of claim 1, wherein an error is reported wherein the undefined function unit is detected. ### Claim 13 (depends on 12) The method of claim 12, wherein the undefined function unit is detected when a move instruction refers to the undefined function unit. ### Claim 14 (depends on 1) The method of claim 1, wherein a function unit is generated to allow a user to provide a definition when the undefined function unit is detected. ### Claim 15 (depends on 1) The method of claim 1, wherein interconnection information specifies how data is moved between the plurality of function units. ### Claim 16 (depends on 1) The method of claim 1, wherein an undefined connection is detected when a move instruction moves data between two function units that are not connected. ### Claim 17 (depends on 16) The method of claim 16, wherein an error is generated when an undefined connection is detected. ### Claim 18 (depends on 16) The method of claim 16, wherein a new path or a new route to an existing multiplexer is created when an undefined connection is detected. ### Claim 19 (depends on 1) The method of claim 1, further comprising providing a custom instruction set associated with the custom processor. ### Claim 20 (depends on 1) The method of claim 1, further comprising automatically generating a test bench for the custom processor. ### Claim 21 (depends on 1) The method of claim 1, further comprising providing the custom processor as a component on a programmable chip system. ### Claim 22 A system for implementing a custom processor, the method comprising: means for receiving a plurality of function units corresponding to components for implementing a signal processing core as an application specific processor, the signal processing core including a Fast Fourier Transform (FFT) data path, wherein the plurality of function units for implementing the signal processing core are selected and parameterized by a user, wherein a function unit is generated to allow a user to provide a definition when the plurality of function units includes an undefined function unit; means for receiving interconnection information for connecting the plurality of function units; and means for generating a hardware description for instantiating the plurality of function units and connecting the plurality of function units. ### Claim 23 A system for implementing a custom processor, the method comprising: an interface configured to receive a plurality of function units corresponding to components for implementing a signal processing core as an application specific processor, the signal processing core including a Fast Fourier Transform (FFT) data path, wherein the plurality of function units for implementing the signal processing core are selected and parameterized by a user; a memory configured to hold information for connecting the plurality of function units; and a processor connected to memory, the processor configured to generate a hardware description for instantiating the plurality of function units and connecting the plurality of function units, wherein a new path or a new route to an existing multiplexer is created when an undefined connection is detected.