# US 7,613,442 B1 · Switch circuit and method of switching radio frequency signals

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- Number: US 7,613,442 B1
- Document ID: US7613442B1
- Status: Granted
- Kind: B1
- Application number: 11/127,520
- Filed: 2005-05-11
- Granted: 2009-11-03
- Earliest claimed: 2001-10-10
- Assignees: Peregrine Semiconductor Corporation
- Inventors: Dylan J. Kelly; Mark L. Burgener; James S. Cable
- Web page: https://patentgrep.com/patent/US7613442B1

## CPC

- H03K 17/063: {in field-effect transistor switches}
- H03K 17/693: Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors (logic circuits H03K19/00; code converters H03M5/00, H03M7/00)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A novel RF switch circuit and method for switching RF signals is described. The RF switch circuit is fabricated in a silicon-on-insulator (SOI) technology. The RF switch includes pairs of switching and shunting transistor groupings used to alternatively couple RF input signals to a common RF node. A fully integrated RF switch is described including digital control logic and a negative voltage generator integrated together with the RF switch elements. In one embodiment, the fully integrated RF switch includes a built-in oscillator, a charge pump circuit, CMOS logic circuitry, level-shifting and voltage divider circuits, and an RF buffer circuit. Several embodiments of the charge pump, level shifting, voltage divider, and RF buffer circuits are described. The RF switch provides improvements in insertion loss, switch isolation, and switch compression. An improved voltage reducing circuit is described. The improved voltage reducing circuit limits voltages applied to selected nodes within the integrated circuit.

## Claims

### Claim 1

An improved voltage reduction circuit adapted to limit voltage levels within an electric circuit, wherein the voltage reduction circuit has an input voltage incident at an input node, an output voltage incident at an output node, and includes a plurality of MOSFET transistors, comprising:
a) a series MOSFET transistor, wherein the series MOSFET transistor has a drain connected to the input node, a gate connected to circuit ground, and a source connected to the output node, and wherein the series MOSFET transistor has a first threshold voltage; and
b) a shunt MOSFET transistor, wherein the shunt MOSFET transistor has a drain connected to the output node, a gate connected to the input node, a source connected to ground, and wherein the shunt MOSFET transistor has a second threshold voltage.

### Claim 2 (depends on 1)

The voltage reduction circuit of claim 1, wherein the series MOSFET transistor comprises an N-channel (NMOS) transistor.

### Claim 3 (depends on 2)

The voltage reduction circuit of claim 2, wherein the shunt MOSFET transistor comprises an N-channel (NMOS) transistor.

### Claim 4 (depends on 1)

The voltage reduction circuit of claim 1, wherein the series MOSFET transistor comprises a P-channel (PMOS) transistor.

### Claim 5 (depends on 4)

The voltage reduction circuit claim 4, wherein the shunt MOSFET transistor comprises a P-channel (PMOS) transistor.

### Claim 6 (depends on 1)

The voltage reduction circuit of claim 1, wherein the first threshold voltage is approximately between 700 mV and 800 mV.

### Claim 7 (depends on 1)

The voltage reduction circuit of claim 1, wherein the second threshold voltage is approximately between 700 mV and 800 mV.

### Claim 8 (depends on 1)

The voltage reduction circuit of claim 1, wherein the input voltage applied to the input node ranges approximately between −3 volts and 0 volts.

### Claim 9 (depends on 1)

The voltage reduction circuit of claim 1, wherein the input voltage at the input node is greater than 0 volts, and wherein the output voltage at the output node is clipped at approximately 0 volts.

### Claim 10 (depends on 1)

The voltage reduction circuit of claim 1, wherein a voltage between the drain and source of the shunt MOSFET transistor comprises a leakage current multiplied by a resistance of the shunt MOSFET transistor.

### Claim 11 (depends on 10)

The voltage reduction circuit of claim 10, wherein the leakage current comprises 1 pA, and wherein the resistance of the shunt MOSFET transistor comprise approximately 2.5K ohms.