# US 7,613,267 B2 · Digitally-synthesized loop filter method and circuit particularly useful for a phase locked loop

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 7,613,267 B2
- Document ID: US7613267B2
- Status: Granted
- Kind: B2
- Application number: 10/895,002
- Filed: 2004-07-20
- Published: 2004-12-30
- Granted: 2009-11-03
- Earliest claimed: 2000-07-10
- Assignees: Silicon Laboratories Inc.
- Inventors: Michael H. Perrott; Rex T. Baird; Yunteng Huang
- Web page: https://patentgrep.com/patent/US7613267B2

## CPC

- H04L 7/033: using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H03L 7/085: concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00)
- H03L 7/087: using at least two phase detectors or a frequency and phase detector in the loop
- H03L 7/091: the phase or frequency detector using a sampling device (H03L7/087 takes precedence)
- H03L 7/093: using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence)
- H03L 7/095: using a lock detector (H03L7/087 takes precedence)
- H04L 7/0004: {Initialisation of the receiver (H04L7/0075 and H04L7/10 take precedence)}
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)

## Abstract

In a feedback system such as a PLL, the integrating function associated with a loop filter capacitor is instead implemented digitally and is easily implemented on the same integrated circuit die as the PLL. There is no need for either an external loop filter capacitor nor for a large loop filter capacitor to be integrated on the same integrated circuit die as the PLL. In some embodiments, an analog phase detector is utilized whose phase error output signal is delta-sigma modulated to encode the magnitude of the phase error using a digital (i.e., discrete-time and discrete-value) signal. This digital phase error signal is “integrated” by a digital integration block including, for example, a digital accumulator, whose output is then converted to an analog signal, optionally combined with a loop feed-forward signal, and then conveyed as a control voltage to the voltage-controlled oscillator. The equivalent “size” of the integrating capacitor function provided by the digital integration block may be varied by increasing or decreasing the bit resolution of circuits within the digital block.

## Claims

### Claim 1

A method for controlling an oscillator in a phase locked loop system, said method comprising:
generating a digital representation of a phase error signal of the phase locked loop system;
generating a multi-bit accumulated digital phase error signal representing an accumulated value of successive values of the digital phase error signal; and
generating an oscillator control signal corresponding to the accumulated digital phase error signal,
wherein the digital phase error signal comprises a quantized-time and quantized-value signal which encodes polarity of phase error.

### Claim 2 (depends on 1)

The method defined by claim 1 wherein the generating the digital representation of the phase error signal comprises:
generating an analog representation of a phase error signal; and
converting the analog phase error signal into a corresponding digital phase error signal.

### Claim 3 (depends on 2)

The method defined by claim 2 wherein the converting step comprises delta-sigma encoding the digital phase error signal.

### Claim 4 (depends on 1)

The method defined by claim 1 wherein the generating a multi-bit accumulated digital phase error signal comprises:
accumulating successive values of a digital input signal representing the phase error, and providing a multi-bit accumulated digital phase error signal.

### Claim 5 (depends on 4)

The method defined by claim 4 wherein:
the oscillator control signal corresponds to a configurable number of bits of the multi-bit accumulated digital phase error signal.

### Claim 6 (depends on 4)

The method defined by claim 4 wherein the accumulating successive values of a digital input signal representing the phase error step comprises:
clocking a lower-order accumulator circuit at a first clock rate, said lower-order accumulator circuit having an input responsive to the digital input signal representing the phase error, and having at least one output; and
clocking an upper-order accumulator circuit at a second clock rate, said upper-order accumulator circuit having an input coupled to an output of the lower-order accumulator circuit, and having an output for conveying a portion of the multi-bit accumulated digital phase error signal;
wherein the respective outputs of the lower-order accumulator circuit and the upper-order accumulator circuit together comprise the multi-bit accumulated digital phase error signal.

### Claim 7 (depends on 6)

The method defined by claim 6 wherein:
the second clock rate is lower than the first clock rate.

### Claim 8 (depends on 6)

The method defined by claim 6 further comprising:
generating the oscillator control signal corresponding to only a portion of the upper-order and lower-order accumulator bits forming the accumulated digital phase error signal.

### Claim 9 (depends on 8)

The method defined by claim 8 wherein:
generating the oscillator control signal corresponding to only upper-order accumulator bits forming the accumulated digital phase error signal.

### Claim 10 (depends on 4)

The method defined by claim 4 further comprising:
decimating the digital phase error signal and accumulating successive values of the decimated digital phase error signal to generate the multi-bit accumulated digital phase error signal.

### Claim 11 (depends on 1)

The method defined by claim 1 wherein the oscillator control signal comprises an analog representation of at least a most-significant-bit portion of the accumulated digital phase error signal.

### Claim 12 (depends on 1)

The method defined by claim 1 further comprising:
providing the oscillator control signal as an analog signal.

### Claim 13 (depends on 12)

The method defined by claim 12 further comprising:
low-pass filtering the analog oscillator control signal.

### Claim 14 (depends on 1)

The method defined by claim 1 further comprising:
configuring a number of bits in the accumulated digital phase error signal to determine an effective value of capacitance within a filter portion of the phase locked loop system.

### Claim 15 (depends on 14)

The method defined by claim 14 further comprising:
varying the number of bits in the accumulated digital phase error signal to alter an operating characteristic of the phase locked loop system.

### Claim 16 (depends on 1)

The method defined by claim 1 implemented entirely within an integrated circuit.

### Claim 17

A method for controlling an oscillator in a phase locked loop system, said method comprising:
generating a digital representation of a phase error signal of the phase locked loop system;
generating a multi-bit accumulated digital phase error signal representing an accumulated value of successive values of the digital phase error signal; and
generating an oscillator control signal corresponding to the accumulated digital phase error signal,
wherein the digital phase error signal comprises a quantized-time and quantized-value signal which linearly encodes phase error.

### Claim 18

A method for controlling an oscillator in a phase locked loop system, said method comprising:
generating a digital representation of a phase error signal of the phase locked loop system;
generating a multi-bit accumulated digital phase error signal representing an accumulated value of successive values of the digital phase error signal; and
generating an oscillator control signal corresponding to the accumulated digital phase error signal,
wherein the multi-bit accumulated digital phase error signal is computed to a greater number of bits than that to which the oscillator control signal corresponds.

### Claim 19

A method for controlling an oscillator in a phase locked loop system, said method comprising:
generating a digital representation of a phase error signal of the phase locked loop system;
generating a multi-bit accumulated digital phase error signal representing an accumulated value of successive values of the digital phase error signal; and
generating an oscillator control signal corresponding to the accumulated digital phase error signal,
wherein the method is implemented entirely within an integrated circuit which is configured to recover clock and data from an incoming data signal having more than one possible data rate, said method further comprising varying the number of bits in the accumulated digital phase error signal based upon the data rate of the incoming data input signal.

### Claim 20 (depends on 19)

The method defined by claim 19 wherein the incoming data input signal is a SONET signal.