# US 7,613,217 B2 · Semiconductor surface emitting device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,613,217 B2 - Document ID: US7613217B2 - Status: Granted - Kind: B2 - Application number: 12/071,170 - Filed: 2008-02-15 - Published: 2008-06-26 - Granted: 2009-11-03 - Earliest claimed: 2003-07-30 - Assignees: Sumitomo Electric Industries, Ltd. - Inventors: Tsukuru Katsuyama; Jun-ichi Hashimoto - Web page: https://patentgrep.com/patent/US7613217B2 ## CPC - H01S 5/18308: {having a special structure for lateral current or light confinement} - H01S 5/2209: {GaInP based} - H01S 5/222: {having a refractive index lower than that of the cladding layers or outer guiding layers} - H01S 5/3211: {characterised by special cladding layers, e.g. details on band-discontinuities} - H01S 5/32366: {(In)GaAs with small amount of N} - H01S: DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL ## Abstract This surface emitting semiconductor device 1 comprises a first conductivity type semiconductor region, an active layer, a second conductivity type semiconductor layer and current block semiconductor region. The first conductivity type semiconductor region is provided on a surface made of GaAs semiconductor. The active layer is provided on the first conductivity type semiconductor region. The active layer has a side surface. The second conductivity type semiconductor layer is provided on the active layer. The second conductivity type semiconductor layer has a side surface. The current block semiconductor region is provided on the side surface of the active layer and on the side surface of the second conductivity type semiconductor layer. The active layer is made of III-V compound semiconductor including at least nitrogen element as a V group element. ## Claims ### Claim 1 A surface emitting semiconductor device comprising: a first conductivity type semiconductor region, provided on a GaAs semiconductor region, including a primary surface having a first area and a second area; a semiconductor mesa including an active layer and a second conductivity type semiconductor layer, said active layer being provided on said first area of said first conductivity type semiconductor region, said second conductivity type semiconductor layer being provided on said active layer, and said semiconductor mesa having a side surface; a current block semiconductor region, provided on said second area of said first conductivity type semiconductor region and said side surface of said semiconductor mesa, for confining carriers to said semiconductor mesa; a first DBR portion having a plurality of first DBR semiconductor layers and a plurality of second DBR semiconductor layers, said first DBR semiconductor layers and said second DBR semiconductor layers being arranged alternately; and a second DBR portion having a plurality of third DBR semiconductor layers and a plurality of fourth DBR semiconductor layers, said third DBR semiconductor layers and said fourth DBR semiconductor layers being arranged alternately; wherein said first conductivity type semiconductor region, said active layer and said second conductivity type semiconductor layer are provided between said first DBR portion and said second DBR portion; wherein said active layer is made of III-V compound semiconductor including at least nitrogen (N) as a V group member; wherein said surface emitting semiconductor device further comprises an additional semiconductor layer made of III-V compound semiconductor; wherein said additional semiconductor layer is provided between said first conductivity type semiconductor region and said active layer; and wherein a photoluminescence wavelength of said III-V compound semiconductor of said additional semiconductor layer is between that of said active layer and that of said first conductivity type semiconductor region. ### Claim 2 (depends on 1) The surface emitting semiconductor device according to claim 1, wherein said first conductivity type semiconductor region is made of semiconductor material enabling said first conductivity type semiconductor region to be an etch stopper resistant to etchant for etching said active layer and said second conductivity type semiconductor layer. ### Claim 3 (depends on 1) The surface emitting semiconductor device according to claim 1, Wherein said III-V compound semiconductor of said active layer contains at least gallium (Ga) as a III group member; and wherein said III-V compound semiconductor of said active layer contains at least arsenic (As) as a V group member. ### Claim 4 (depends on 1) The surface emitting semiconductor device according to claim 1, wherein said active layer is made of at least one of GaInNAs semiconductor, GaNAs semiconductor, GaNAsSb semiconductor, GaNAsP semiconductor, GaNAsSbP semiconductor, GaInNAsSb semiconductor, GaInNAsP semiconductor and GaInNAsSbP semiconductor. ### Claim 5 (depends on 1) The surface emitting semiconductor device according to claim 1, wherein said second conductivity type semiconductor layer has a refractive index higher than that of said current block semiconductor region. ### Claim 6 (depends on 1) The surface emitting semiconductor device according to claim 1, wherein said current block semiconductor region includes first and second current block layers; wherein said first conductivity type semiconductor region is made of (AlX1Ga1-X1)Y1In1-Y1P semiconductor, where a composition X1 has a value in a range of zero or greater but not greater than 1; wherein said second conductivity type semiconductor layer is made of (AlX2Ga1-X2)Y2In1-Y2P semiconductor, where a composition X2 has a value in a range of zero or greater but not greater than 1; and wherein said first and second current block layers are made of (AlX3Ga1-X3)Y3In1-Y3P semiconductor, where a composition X3 has a value in a range of zero or greater but not greater than 1. ### Claim 7 (depends on 1) The surface emitting semiconductor device according to claim 1, wherein said current block semiconductor region includes first and second current block layers; wherein said first conductivity type semiconductor region is made of an AlX1Ga1-X1As semiconductor, where a composition X1 has a value in a range of zero or greater but not greater than 1; wherein said second conductivity type semiconductor layer is made of an AlX2Ga1-X2As semiconductor, where a composition X2 has a value in a range of zero or greater but not greater than 1; and wherein said first and second current block layers are made of AlX3Ga1-X3As semiconductor, where a composition X3 has a value in a range of zero or greater but not greater than 1. ### Claim 8 (depends on 1) The surface emitting semiconductor device according to claim 1, wherein said GaAs semiconductor region is provided by one of a GaAs semiconductor layer and a gallium arsenide substrate. ### Claim 9 (depends on 1) The surface emitting semiconductor device according to claim 1, wherein said surface emitting semiconductor device is constituted to provide at least one of a semiconductor laser diode and a semiconductor optical amplifier. ### Claim 10 A surface emitting semiconductor device comprising: a first conductivity type semiconductor region, provided on a GaAs semiconductor region, including a primary surface having a first area and a second area; a semiconductor mesa including an active layer and a second conductivity type semiconductor layer, said active layer being provided on said first area of said first conductivity type semiconductor region, said second conductivity type semiconductor layer being provided on said active layer, and said semiconductor mesa having a side surface; a current block semiconductor region, provided on said second area of said first conductivity type semiconductor region and said side surface of said semiconductor mesa, for confining carriers to said semiconductor mesa; a first DBR portion having a plurality of first DBR semiconductor layers and a plurality of second DBR semiconductor layers, said first DBR semiconductor layers and said second DBR semiconductor layers being arranged alternately; and a second DBR portion having a plurality of third DBR semiconductor layers and a plurality of fourth DBR semiconductor layers, said third DBR semiconductor layers and said fourth DBR semiconductor layers being arranged alternately; wherein said first conductivity type semiconductor region, said active layer and said second conductivity type semiconductor layer are provided between said first DBR portion and said second DBR portion; wherein said active layer is made of III-V compound semiconductor including at least nitrogen (N) as a V group member; wherein said surface emitting semiconductor device further comprises an additional semiconductor layer made of III-V compound semiconductor; wherein said additional semiconductor layer is provided between said second conductivity type semiconductor layer and said active layer; and wherein a photoluminescence wavelength of said III-V compound semiconductor of said additional semiconductor layer is between that of said active layer and that of said second conductivity type semiconductor layer. ### Claim 11 A surface emitting semiconductor device comprising: a first conductivity type semiconductor region, provided on a GaAs semiconductor region, including a primary surface having a first area and a second area; a semiconductor mesa including an active layer and a second conductivity type semiconductor layer, said active layer being provided on said first area of said first conductivity type semiconductor region, said second conductivity type semiconductor layer being provided on said active layer, and said semiconductor mesa having a side surface; a current block semiconductor region, provided on said second area of said first conductivity type semiconductor region and said side surface of said semiconductor mesa, for confining carriers to said semiconductor mesa; a first DBR portion having a plurality of first DBR semiconductor layers and a plurality of second DBR semiconductor layers, said first DBR semiconductor layers and said second DBR semiconductor layers being arranged alternately; and a second DBR portion having a plurality of third DBR semiconductor layers and a plurality of fourth DBR semiconductor layers, said third DBR semiconductor layers and said fourth DBR semiconductor layers being arranged alternately; wherein said first conductivity type semiconductor region, said active layer and said second conductivity type semiconductor layer are provided between said first DBR portion and said second DBR portion; wherein said active layer is made of III-V compound semiconductor including at least nitrogen (N) as a V group member; wherein said surface emitting semiconductor device further comprises a first SCH layer provided between said first conductivity type semiconductor region and said active layer; and a second SCH layer provided between said active layer and said second conductivity type semiconductor layer. ### Claim 12 (depends on 11) The surface emitting semiconductor device according to claim 11, further comprising an additional semiconductor layer made of III-V compound semiconductor; wherein said additional semiconductor layer is provided between said first conductivity type semiconductor region and said first SCH layer; and wherein a photoluminescence wavelength of said III-V compound semiconductor of said additional semiconductor layer is between that of said first SCH layer and that of said first conductivity type semiconductor layer. ### Claim 13 (depends on 11) The surface emitting semiconductor device according to claim 11, further comprising an additional semiconductor layer made of III-V compound semiconductor; wherein said additional semiconductor layer is provided between said second conductivity type semiconductor layer and said second SCH layer; wherein a photoluminescence wavelength of said III-V compound semiconductor of said additional semiconductor layer is between that of said second SCH layer and that of said second conductivity type semiconductor layer. ### Claim 14 A surface emitting semiconductor device comprising: a first conductivity type semiconductor region, provided on a GaAs semiconductor region, including a primary surface having a first area and a second area; a semiconductor mesa including an active layer and a second conductivity type semiconductor layer, said active layer being provided on said first area of said first conductivity type semiconductor region, said second conductivity type semiconductor layer being provided on said active layer, and said semiconductor mesa having a side surface; a current block semiconductor region, provided on said second area of said first conductivity type semiconductor region and said side surface of said semiconductor mesa, for confining carriers to said semiconductor mesa; a first DBR portion having a plurality of first DBR semiconductor layers and a plurality of second DBR semiconductor layers, said first DBR semiconductor layers and said second DBR semiconductor layers being arranged alternately; and a second DBR portion having a plurality of third DBR semiconductor layers and a plurality of fourth DBR semiconductor layers, said third DBR semiconductor layers and said fourth DBR semiconductor layers being arranged alternately; wherein said first conductivity type semiconductor region, said active layer and said second conductivity type semiconductor layer are provided between said first DBR portion and said second DBR portion; wherein said active layer is made of III-V compound semiconductor including at least nitrogen (N) as a V group member; wherein said surface emitting semiconductor device further comprises a first SCH layer provided between said first conductivity type semiconductor region and said active layer; and a second SCH layer provided between said active layer and said second conductivity type semiconductor layer; and wherein said first and second SCH layers are made of one of AlX1Ga1-X1As semiconductor (0≦X1≦1) and GaX2In1-X2AsY2P1-Y2 semiconductor (about 0.5≦X2≦1, 0≦Y2≦1) lattice-matched to GaAs semiconductor. ### Claim 15 A surface emitting semiconductor device comprising: a first conductivity type semiconductor region, provided on a GaAs semiconductor region, including a primary surface having a first area and a second area; a semiconductor mesa including an active layer and a second conductivity type semiconductor layer, said active layer being provided on said first area of said first conductivity type semiconductor region, said second conductivity type semiconductor layer being provided on said active layer, and said semiconductor mesa having a side surface; a current block semiconductor region, provided on said second area of said first conductivity type semiconductor region and said side surface of said semiconductor mesa, for confining carriers to said semiconductor mesa; a first DBR portion having a plurality of first DBR semiconductor layers and a plurality of second DBR semiconductor layers, said first DBR semiconductor layers and said second DBR semiconductor layers being arranged alternately; and a second DBR portion having a plurality of third DBR semiconductor layers and a plurality of fourth DBR semiconductor layers, said third DBR semiconductor layers and said fourth DBR semiconductor layers being arranged alternately; wherein said first conductivity type semiconductor region, said active layer and said second conductivity type semiconductor layer are provided between said first DBR portion and said second DBR portion; wherein said active layer is made of III-V compound semiconductor including at least nitrogen (N) as a V group member; wherein said current block semiconductor region includes first and second current block layers; and wherein said first and second current block semiconductor layers are made of material not containing aluminum as a III group element. ### Claim 16 The surface emitting semiconductor device comprising: a first conductivity type semiconductor region, provided on a GaAs semiconductor region, including a primary surface having a first area and a second area; a semiconductor mesa including an active layer and a second conductivity type semiconductor layer, said active layer being provided on said first area of said first conductivity type semiconductor region, said second conductivity type semiconductor layer being provided on said active layer, and said semiconductor mesa having a side surface; a current block semiconductor region, provided on said second area of said first conductivity type semiconductor region and said side surface of said semiconductor mesa, for confining carriers to said semiconductor mesa; a first DBR portion having a plurality of first DBR semiconductor layers and a plurality of second DBR semiconductor layers, said first DBR semiconductor layers and said second DBR semiconductor layers being arranged alternately; and a second DBR portion having a plurality of third DBR semiconductor layers and a plurality of fourth DBR semiconductor layers, said third DBR semiconductor layers and said fourth DBR semiconductor layers being arranged alternately; wherein said first conductivity type semiconductor region, said active layer and said second conductivity type semiconductor layer are provided between said first DBR portion and said second DBR portion; wherein said active layer is made of III-V compound semiconductor including at least nitrogen (N) as a V group member; wherein said current block semiconductor region includes first and second current block layers; wherein said first and second current block semiconductor layers are made of material not containing aluminum as a III group element; wherein said first conductivity type semiconductor region is made of material not containing aluminum as a III group element; and wherein said second conductivity type semiconductor layer is made of material not containing aluminum as a III group element. ### Claim 17 A surface emitting semiconductor device comprising: a first conductivity type semiconductor region, provided on a GaAs semiconductor region, including a primary surface having a first area and a second area; a semiconductor mesa including an active layer and a second conductivity type semiconductor layer, said active layer being provided on said first area of said first conductivity type semiconductor region, said second conductivity type semiconductor layer being provided on said active layer, and said semiconductor mesa having a side surface; a current block semiconductor region, provided on said second area of said first conductivity type semiconductor region and said side surface of said semiconductor mesa, for confining carriers to said semiconductor mesa; a first DBR portion having a plurality of first DBR semiconductor layers and a plurality of second DBR semiconductor layers, said first DBR semiconductor layers and said second DBR semiconductor layers being arranged alternately; and a second DBR portion having a plurality of third DBR semiconductor layers and a plurality of fourth DBR semiconductor layers, said third DBR semiconductor layers and said fourth DBR semiconductor layers being arranged alternately; wherein said first conductivity type semiconductor region, said active layer and said second conductivity type semiconductor layer are provided between said first DBR portion and said second DBR portion; wherein said active layer is made of III-V compound semiconductor including at least nitrogen (N) as a V group member; and wherein said GaAs semiconductor region is provided between said first DBR portion and said active layer. ### Claim 18 A surface emitting semiconductor device comprising: a first conductivity type semiconductor region, provided on a GaAs semiconductor region, including a primary surface having a first area and a second area; a semiconductor mesa including an active layer and a second conductivity type semiconductor layer, said active layer being provided on said first area of said first conductivity type semiconductor region, said second conductivity type semiconductor layer being provided on said active layer, and said semiconductor mesa having a side surface; a current block semiconductor region, provided on said second area of said first conductivity type semiconductor region and said side surface of said semiconductor mesa, for confining carriers to said semiconductor mesa; a first DBR portion having a plurality of first DBR semiconductor layers and a plurality of second DBR semiconductor layers, said first DBR semiconductor layers and said second DBR semiconductor layers being arranged alternately; and a second DBR portion having a plurality of third DBR semiconductor layers and a plurality of fourth DBR semiconductor layers, said third DBR semiconductor layers and said fourth DBR semiconductor layers being arranged alternately; wherein said first conductivity type semiconductor region, said active layer and said second conductivity type semiconductor layer are provided between said first DBR portion and said second DBR portion; wherein said active layer is made of III-V compound semiconductor including at least nitrogen (N) as a V group member; and wherein said second DBR portion is provided between said first DBR portion and said GaAs semiconductor region.