# US 7,613,213 B2 · Time multiplexed SONET line processing > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,613,213 B2 - Document ID: US7613213B2 - Status: Granted - Kind: B2 - Application number: 11/209,230 - Filed: 2005-08-23 - Published: 2006-02-23 - Granted: 2009-11-03 - Earliest claimed: 2004-08-23 - Assignees: TranSwitch Corporation - Inventors: Pushkal Yadav; Kumar Shakti Singh; Chitra Wadhwa; Sachin Mathur; Ashis Maitra; Amandeep Singh Gujral; Diljit Singh; Yudhishthira Kundu - Web page: https://patentgrep.com/patent/US7613213B2 ## CPC - H04J 3/1611: {Synchronous digital hierarchy [SDH] or SONET (H04J3/1664 takes precedence for interactions with OTN)} - H04J 3/04: Distributors combined with modulators or demodulators {(pulse distributors in general H03K5/15; pulse counters H03K21/00 - H03K29/06; for telegraphy H04L5/22, H04L13/00 - H04L23/00, H04L25/45; for telephony H04Q11/04)} - H04J 3/0685: {Clock or time synchronisation in a node; Intranode synchronisation} - H04J: MULTIPLEX COMMUNICATION (transmission in general H04B; peculiar to transmission of digital information H04L5/00; systems for the simultaneous or sequential transmission of more than one television signal H04N7/08; in exchanges H04Q11/00; stereophonic systems H04S) ## Abstract Time multiplexed processing of multiple SONET signals uses the same shared circuitry for framing, descrambling, maintenance signal processing, control byte processing and extraction, pointer tracking, retiming, and alarm indication. The signals are deserialized and multiplexed onto a byte-wide bus from which they are processed in a shared pipeline. Additional pipelines allow scaling up to higher capacity SONET signals. Each pipeline is provided with means for communicating with the other pipelines so that information derived from the processing of one stream can be shared with the processing of other streams when necessary. According to the presently preferred embodiment, bytes pass through the pipeline in five clock cycles. ## Claims ### Claim 1 A method for processing n number of SONET STS streams, where n is an integer greater than two, comprising: deserializing each of the n number of streams; buffering each deserialized stream; generating a time wheel clock having a frequency greater than the aggregate deserialized data rate; generating a plurality of clock signals synchronous to the time wheel clock, the plurality of signals each representing a plurality of time slots that include time slots corresponding to the n number of streams as well as a number of spare time slots; utilizing at least one of the clock signals to multiplex the n streams over a parallel databus during the time slots corresponding to the n streams and generate a control signal that no valid data is present on the parallel databus during the spare time slots; and processing the multiplexed n streams in a pipeline, wherein the pipeline includes a plurality of shared circuits operating at the time wheel clock frequency. ### Claim 2 (depends on 1) The method according to claim 1, wherein: said processing includes at least two processes selected from the group consisting of framing, descrambling, and pointer tracking. ### Claim 3 (depends on 1) The method according to claim 1, wherein: (n times p) streams are processed, p being an integer, and said streams are processed using p pipelines with n streams being processed in each of the pipelines. ### Claim 4 (depends on 1) The method according to claim 1, further comprising: providing a communication circuit and communicating information among said plurality of circuits. ### Claim 5 (depends on 3) The method according to claim 3, further comprising: providing a communication circuit in each pipeline and a communication bus coupling the communication circuits, and communicating information among said p pipelines. ### Claim 6 (depends on 1) The method according to claim 1, wherein: said n number of STS streams are contained in a single SONET STS-n signal. ### Claim 7 (depends on 1) The method according to claim 1, wherein: said n number of STS streams are contained in multiple SONET STS-M signals, where M is a factor of n. ### Claim 8 (depends on 3) The method according to claim 3, wherein: said (n times p) streams are contained in a single SONET STS-(n times p) signal. ### Claim 9 (depends on 3) The method according to claim 3, wherein: said (n times p) streams are contained in multiple SONET STS-M signals, where M is a factor of (n times p). ### Claim 10 (depends on 5) The method according to claim 5, wherein: the information is BIP-8 information. ### Claim 11 (depends on 5) The method according to claim 5, wherein: the information is pointer information. ### Claim 12 An apparatus for processing n number of SONET STS streams, where n is an integer greater than two, comprising: a multi-stream processing apparatus which includes n number of serial to parallel converters having outputs outputting n number of byte wide data streams, said data streams having an aggregate data rate; n number of buffers, each coupled to a respective output of a serial to parallel converter, said buffers having outputs outputting n number of buffered data streams; a multiplexer coupled to said outputs of said n number of buffers, said multiplexer having an output outputting byte wide multiplexed data; a byte-wide parallel data bus coupled to the output of said multiplexer; a pipeline of processing circuits coupled to said data bus; a time wheel clock generator generating a time wheel clock having a frequency greater than the aggregate data rate; and a clock signal generator generating a plurality of clock signals synchronous to the time wheel clock, the plurality of signals each representing a plurality of time slots that include time slots corresponding to the n number of data streams as well as a number of spare time slots, wherein the buffers utilize at least one of the clock signals to output the buffered data streams to the multiplexer for multiplexing the n streams over the byte-wide parallel data bus during the time slots corresponding to the n data streams, and a data valid generator utilizes at least one of the clock signals to generate a control signal that no valid data is present on the byte-wide parallel data bus during the spare time slots; and said time wheel clock is supplied to said pipeline of processing circuits. ### Claim 13 (depends on 12) The apparatus according to claim 12, wherein: said pipeline of processing circuits includes at least two circuits selected from the group consisting of a framer, a descrambler, and a pointer tracker. ### Claim 14 (depends on 12) The apparatus according to claim 12, wherein: said apparatus includes p number of multi-stream processing apparatus, where p is an integer greater than one and said apparatus processes (n times p) STS streams. ### Claim 15 (depends on 12) The apparatus according to claim 12, further comprising: a communication circuit coupled to said pipeline of processing circuits for communicating information among said plurality of processing circuits. ### Claim 16 (depends on 14) The apparatus according to claim 14, further comprising: p number of communication circuits, each being coupled to a respective pipeline of circuits; and a communication bus coupled to each of the communication circuits, wherein information is communicated among said p pipelines. ### Claim 17 (depends on 12) The apparatus according to claim 12, wherein: said n number of STS streams are contained in a single SONET STS-n signal. ### Claim 18 (depends on 12) The apparatus according to claim 12, wherein: said n number of STS streams are contained in multiple SONET STS-M signals, where M is a factor of n. ### Claim 19 (depends on 14) The apparatus according to claim 14, wherein: said (n times p) streams are contained in a single SONET STS-(n times p) signal. ### Claim 20 (depends on 14) The apparatus according to claim 14, wherein: said (n times p) streams are contained in multiple SONET STS-m signals, where m is a factor of (n times p). ### Claim 21 (depends on 12) The apparatus according to claim 12, wherein: said apparatus is provided on a single chip.