# US 7,613,164 B2 · Method and apparatus for generating and distributing an internal clock for radio network controller > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,613,164 B2 - Document ID: US7613164B2 - Status: Granted - Kind: B2 - Application number: 10/979,168 - Filed: 2004-11-03 - Published: 2005-07-07 - Granted: 2009-11-03 - Earliest claimed: 2003-11-04 - Assignees: Alcatel - Inventors: Li Chunxu; Vianney Andrieu; Liu Weiwei; Marc Freynet; Li Qing; Pierre Delbreil; Alf Neustadt - Web page: https://patentgrep.com/patent/US7613164B2 ## CPC - H04J 3/0688: {Change of the master or reference, e.g. take-over or failure of the master} - H04J 3/0691: {Synchronisation in a TDM node} - H04J: MULTIPLEX COMMUNICATION (transmission in general H04B; peculiar to transmission of digital information H04L5/00; systems for the simultaneous or sequential transmission of more than one television signal H04N7/08; in exchanges H04Q11/00; stereophonic systems H04S) ## Abstract A method for generating an internal clock in a radio network controller and a relevant transmission processing board. The transmission processing board comprises; a clock signal selector for extracting a clock signal from a synchronous/asynchronous line connected with a core network when said transmission processing board functions as a master transmission processing board, or for obtaining a clock signal from a clock bus of a sub-rack in which said transmission processing board is located when said transmission processing board functions as a slave transmission processing board; a phase-locked loop for generating a reference transmission clock based on the clock signal extracted or obtained by said clock signal selector; and a clock driver for transmitting the generated reference transmission clock to the clock bus of the sub-rackin which said transmission processing board is located when said transmission processing board functions as a master transmission processing board. ## Claims ### Claim 1 A method for generating an internal clock in a radio network controller, comprising: extracting, on one of a plurality of transmission processing boards that generate clock signals comprised by said radio network controller, hereinafter master transmission processing board, a clock signal from a synchronous/asynchronous line connected with a core network; generating, on said master transmission processing board, a reference transmission clock based on said clock signal extracted from the said synchronous/asynchronous line; and transmitting said reference transmission clock to a clock bus of a sub-rack in which said master transmission processing board is located. ### Claim 2 (depends on 1) The method for generating an internal clock according to claim 1, further comprising: transmitting said reference transmission clock generated by said master transmission processing board from said clock bus of the sub-rack in which said master transmission processing board is located to a clock bus of another sub-rack. ### Claim 3 (depends on 2) The method for generating an internal clock according to claim 2, further comprising: obtaining a clock signal from said clock bus of another sub-rack on a slave transmission processing board connected with said clock bus; generating a reference transmission clock on said slave transmission processing board based on the clock signal obtained from said clock bus, wherein said reference transmission clock is used internally in said slave transmission processing board. ### Claim 4 A method for generating an internal clock in a radio network controller, comprising: extracting, on a master transmission processing board, a clock signal from a synchronous/asynchronous line connected with a core network; generating, on said master transmission processing board, a reference transmission clock based on said clock signal extracted from the said synchronous/asynchronous line; and transmitting said reference transmission clock to a clock bus of a sub-rack in which said master transmission processing board is located in case of said master transmission processing board cannot extract the clock signal from said synchronous/asynchronous line, an Operation & Maintenance center in said radio network controller selecting a slave transmission processing board connected with said core network to function as a master transmission processing board. ### Claim 5 A method for generating an internal clock in a radio network controller, comprising: generating, on a specified transmission processing board, a reference transmission clock; counting, on said specified transmission processing board, said reference transmission clock to generate a radio clock; broadcasting periodically said radio clock from said specified transmission processing board to at least one radio processing board in said radio network controller, wherein said generating the reference transmission clock further comprises: extracting a clock signal from a synchronous/asynchronous line connected with the core network on said specified transmission processing board; generating said reference transmission clock on said specified transmission processing board based on the clock signal extracted from said synchronous/asynchronous line. ### Claim 6 (depends on 5) The method for generating an internal clock according to claim 5, wherein said generating the reference transmission clock further comprises: obtaining a clock signal from a connected clock bus on another transmission processing board; generating said reference transmission clock on the said another transmission processing board based on the clock signal obtained from said clock bus. ### Claim 7 (depends on 5) The method for generating an internal clock according to claim 5, further comprising: in case of said specified transmission processing board fails, an Operation & Maintenance center of said radio network controller selecting another transmission processing board connected with said clock bus as said specified transmission processing board. ### Claim 8 A transmission processing board for a radio network controller, comprising: a clock signal selector for extracting a clock signal from a synchronous/asynchronous line connected with a core network when said transmission processing board functions as a master transmission processing board, and for obtaining a clock signal from a clock bus of a sub-rack in which said transmission processing board is located when said transmission processing board functions as a slave transmission processing board; a phase-locked loop for generating a reference transmission clock based on the clock signal extracted or obtained by said clock signal selector; and a clock driver for transmitting the generated reference transmission clock to the clock bus of the sub-rack in which said transmission processing board is located when said transmission processing board functions as a master transmission processing board. ### Claim 9 (depends on 8) The transmission processing board according to claim 8, further comprising: a cable for connecting clock buses of different sub-racks in said radio network controller. ### Claim 10 (depends on 9) The transmission processing board according to claim 9, further comprising: an additional clock driver for obtaining a clock signal from the clock bus of the sub-rack in which said transmission processing board is located and transferring the obtained clock signal to said clock signal selector when said transmission processing board functions as a slave transmission processing board. ### Claim 11 A transmission processing board for a radio network controller, comprising: a reference transmission clock generator; a radio clock generator for counting said reference transmission clock and generating a radio clock; a Network Time Protocol/Simple Network Time Protocol server for broadcasting periodically said radio clock from said transmission processing board to at least one radio processing board in said radio network controller. ### Claim 12 (depends on 11) The transmission processing board according to claim 11, wherein the reference transmission clock generator comprises: a clock signal selector for extracting a clock signal from a synchronous/asynchronous line connected with a core network; and a phase-locked loop for generating said reference transmission clock based on the clock signal extracted by said clock signal selector. ### Claim 13 (depends on 11) The transmission processing board according to claim 11, wherein said reference transmission clock generator comprises: a clock signal selector for obtaining a clock signal from a clock bus of the sub-rack in which said transmission processing board is located; and a phase-locked loop for generating said reference transmission clock based on the clock signal obtained by said clock signal selector.