# US 7,613,061 B2 · Method and apparatus for idle cycle refresh request in DRAM > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,613,061 B2 - Document ID: US7613061B2 - Status: Granted - Kind: B2 - Application number: 11/948,214 - Filed: 2007-11-30 - Published: 2009-06-04 - Granted: 2009-11-03 - Earliest claimed: 2007-11-30 - Assignees: Agere Systems Inc. - Inventors: Ross A. Kohler; Richard J McPartland; Wayne E Werner - Web page: https://patentgrep.com/patent/US7613061B2 ## CPC - G11C 11/406: Management or control of the refreshing or charge-regeneration cycles - G11C 2211/4061: Calibration or ate or cycle tuning - G11C 2211/4065: Low level details of refresh operations - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Generally, methods and apparatus are provided for idle cycle refresh request in a dynamic random access memory. According to one aspect of the invention, a dynamic random access memory is refreshed by determining if a refresh of the dynamic random access memory is required; and allocating an idle cycle sequence to refresh at least a portion of the dynamic random access memory only if the determining step determines that a refresh of the dynamic random access memory is required. A refresh flag can optionally be set if a refresh is required. The idle cycle sequence comprises one or more idle cycles. The idle cycle sequence can optionally be allocated within a predefined duration of the refresh flag being set. The step of determining step whether a refresh of the dynamic random access memory is required can be based on real-time or expected conditions. ## Claims ### Claim 1 A method for refreshing a dynamic random access memory, comprising: determining if a refresh of said dynamic random access memory is required; and allocating an idle cycle sequence to refresh at least a portion of said dynamic random access memory only if said determining step determines that a refresh of said dynamic random access memory is required; wherein said determining step determines if a refresh of said dynamic random access memory is required based on real-time conditions. ### Claim 2 (depends on 1) The method of claim 1, further comprising the step of setting a refresh flag if a refresh is required. ### Claim 3 (depends on 1) The method of claim 1, wherein said idle cycle sequence comprises one or more idle cycles. ### Claim 4 (depends on 1) The method of claim 1, wherein said idle cycle sequence comprises at least one cycle for a read or write operation between two idle cycles. ### Claim 5 (depends on 1) The method of claim 1, wherein said allocating step allocates said idle cycle sequence within a predefined duration of said refresh flag being set. ### Claim 6 (depends on 5) The method of claim 5, wherein said predefined duration is a next cycle after said refresh flag is set. ### Claim 7 (depends on 1) The method of claim 1, wherein said real-time conditions comprise one or more of real-time charge leakage, operating temperature and operating voltage. ### Claim 8 (depends on 1) The method of claim 1, wherein said determining step further determines if a refresh of said dynamic random access memory is required based on expected conditions. ### Claim 9 (depends on 8) The method of claim 8, wherein said expected conditions comprise one or more of charge leakage, operating temperature and operating voltage. ### Claim 10 A logic system for refreshing a dynamic random access memory, comprising: a logic circuit for determining if a refresh of the dynamic random access memory is required; and a logic circuit for allocating an idle cycle sequence to refresh at least a portion of the dynamic random access memory only if the determining step determines that a refresh of the dynamic random access memory is required; wherein the logic circuit for determining determines if a refresh of the dynamic random access memory is required based on real-time conditions. ### Claim 11 (depends on 10) The logic system of claim 10, further comprising a logic circuit to set a refresh flag if a refresh is required. ### Claim 12 (depends on 10) The logic system of claim 10, wherein the idle cycle sequence comprises at least one cycle for a read or write operation between two idle cycles. ### Claim 13 (depends on 10) The logic system of claim 10, wherein the logic circuit for allocating allocates the idle cycle sequence within a predefined duration of the refresh flag being set. ### Claim 14 (depends on 10) The logic system of claim 10, wherein the real-time conditions comprise one or more of real-time charge leakage, operating temperature and operating voltage. ### Claim 15 (depends on 10) The logic system of claim 10, wherein the logic circuit for determining further determines if a refresh of the dynamic random access memory is required based on expected conditions. ### Claim 16 (depends on 15) The logic system of claim 15, wherein the expected conditions comprise one or more of charge leakage, operating temperature and operating voltage. ### Claim 17 A system for refreshing a dynamic random access memory, comprising: a memory; and at least one processor, coupled to the memory, operative to: determine if a refresh of said dynamic random access memory is required; and allocate an idle cycle sequence to refresh at least a portion of said dynamic random access memory only if said determining step determines that a refresh of said dynamic random access memory is required; wherein said processor determines if a refresh of said dynamic random access memory is required based on real-time conditions. ### Claim 18 (depends on 17) The system of claim 17, wherein said processor further determines if a refresh of said dynamic random access memory is required based on expected conditions.