# US 7,613,055 B2 · Programmable control block for dual port SRAM application > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,613,055 B2 - Document ID: US7613055B2 - Status: Granted - Kind: B2 - Application number: 11/836,639 - Filed: 2007-08-09 - Published: 2009-02-12 - Granted: 2009-11-03 - Earliest claimed: 2007-08-09 - Assignees: Altera Corporation - Inventors: Catherine Chingi Chang - Web page: https://patentgrep.com/patent/US7613055B2 ## CPC - G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management - G11C 8/16: Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups - G11C 11/413: Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A dual-port static random access memory (SRAM) includes a multitude of programmable delay elements disposed along the paths of a number signals used to carry out read, write or read-then-write operations. At least one of the programmable delay elements controls the timing margin between a pair of clock signals that trigger a read/write enable signal. A second programmable delay element coarsely adjusts the delay of a first signal associated with a dummy bitline. A third programmable delay element finely adjusts the delay of a second signal associated with the dummy bitline. A fourth programmable delay element controls the delay of a signal used to reset the read/write enable signal. During a read operation, the voltage level of the second signal is used as an indicator to activate the sense amplifiers. During a write operation, the voltage level of the second signal is used to control the write cycle. ## Claims ### Claim 1 A memory device comprising: a first plurality of delay elements adapted to delay a second clock signal relative to a first clock signal, the second clock signal being operative to trigger memory access operations; a second plurality of delay elements adapted to vary a delay in accordance with which a signal line associated with a dummy bit line of the memory device responds to a data stored in an associated dummy memory cell; and a sense amplifier adapted to be activated to perform a read operation when the voltage of the signal line reaches a first value. ### Claim 2 (depends on 1) The memory device of claim 1 wherein said second plurality of delay elements are used for fine adjustment of the delay, the memory device further comprising: a third plurality of delay elements adapted for coarse adjustment of a second delay in accordance with which a second signal line associated with the dummy bit line responds to the data stored in the associated dummy memory cell. ### Claim 3 (depends on 2) The memory device of claim 2 wherein said second plurality of delay elements introduce a fine delay before the dummy bit line is accessed. ### Claim 4 (depends on 3) The memory device of claim 3 wherein said third plurality of delay elements introduce a coarse delay after the dummy bit line is accessed. ### Claim 5 (depends on 4) The memory device of claim 4 further comprising a wordline that is responsive to the second signal line, said wordline being adapted to couple a memory cell to a pair of associated true and complementary bitlines when the wordline is selected. ### Claim 6 (depends on 5) The memory device of claim 5 further comprising: a first sequential logic block adapted to receive the first clock signal at its clock input terminal and a read request signal at its data input terminal; and a second sequential logic block adapted to receive the first clock signal at its clock input terminal and a write request signal at its data input terminal. ### Claim 7 (depends on 6) The memory device of claim 6 further comprising a signal generation block adapted to receive the output signals of the first and second sequential logic blocks at its first and second input terminals; the signal generation block further adapted to receive the delayed replica of the second clock signal at its clock input terminal; the signal generation block being reset in response to a first feedback signal, the signal generation block being adapted to generate a memory enable signal operative to trigger memory access operations. ### Claim 8 (depends on 7) The memory device of claim 7 further comprising a fourth plurality of delay elements adapted to delay a signal received from the third plurality of delay elements to generate the first feedback signal. ### Claim 9 (depends on 8) The memory device of claim 8 further comprising a control block adapted to receive the memory enable signal, the output signals of the first and second sequential logic blocks, and the second signal line, and to generate in response a plurality of signals controlling the memory access operations. ### Claim 10 (depends on 9) The memory device of claim 9 wherein said memory device is a static random access memory. ### Claim 11 (depends on 10) The memory device of claim 10 wherein said static random access memory is a dual-port static random access memory. ### Claim 12 (depends on 11) The memory device of claim 11 wherein said dual-port static random access is disposed in an FPGA. ### Claim 13 (depends on 12) The memory device of claim 12 wherein the first, second, third and fourth plurality of delay elements are programmed during a cycle when the FPGA is configured to perform a user defined function. ### Claim 14 A method of operating a memory, the method comprising: delaying a second clock signal relative to a first clock signal; the second clock signal being operative to trigger memory access operations; varying a delay in accordance with which a signal line associated with a dummy bit line of the memory device responds to a data stored in an associated dummy memory cell; and activating a sense amplifier during a read cycle when the voltage of the dummy signal line reaches a first value. ### Claim 15 (depends on 14) The method of claim 14 wherein said delay is varied using fine adjustments, the method further comprising: varying a second delay in accordance with which a second signal line associated with the dummy bit line responds to the data stored in the associated dummy memory cell, wherein said second delay is varied using coarse adjustments. ### Claim 16 (depends on 15) The method of claim 15 wherein said fine adjustments are made before a dummy bit line is accessed. ### Claim 17 (depends on 16) The method of claim 16 wherein said coarse adjustments are made after the dummy bit line is accessed. ### Claim 18 (depends on 17) The method of claim 17 further comprising: selecting a wordline in response to the second signal line's response to the data stored in the associated dummy memory cell; and coupling a memory cell to a pair of associated true and complementary bitlines in response to the selection of the wordline. ### Claim 19 (depends on 18) The method of claim 18 further comprising: supplying the first clock signal to a first sequential logic block adapted to receive a read request signal at its data input terminal; and supplying the first clock signal to a second sequential logic block adapted to receive a write request signal at its data input terminal. ### Claim 20 (depends on 19) The method of claim 19 further comprising: receiving output signals of the first and second sequential logic blocks receiving the delayed replica of the second clock signal; performing a signal reset in response to a first feedback signal; and generating a memory enable signal operative to trigger memory access operations. ### Claim 21 (depends on 20) The method of claim 20 further comprising: delaying the second signal line to generate the first feedback signal. ### Claim 22 (depends on 20) The method of claim 20 further comprising: receiving the memory enable signal; receiving output signals of the first and second sequential logic blocks; receiving the second signal; and generating a plurality of signals controlling the memory access operations in response. ### Claim 23 (depends on 22) The method of claim 22 wherein said memory is a static random access memory. ### Claim 24 (depends on 23) The method of claim 23 wherein said static random access memory is a dual-port static random access memory. ### Claim 25 (depends on 24) The method of claim 24 wherein said dual-port static random access memory is disposed in an FPGA. ### Claim 26 (depends on 25) The method of claim 25 wherein delay adjustment of the second clock, and the coarse and fine delay adjustments of the second and first signal lines, respectively, are performed during a cycle when the FPGA is configured to perform a user defined function. ### Claim 27 A method of operating a memory, the method comprising: varying a first delay in accordance with which a signal line associated with a dummy bit line of the memory device responds to a data stored in an associated dummy memory cell; varying a second delay in accordance with which a second signal line associated with the dummy bit line responds to the data stored in the associated dummy memory cell, wherein said second delay is varied using adjustment that is coarser than said first delay; and resetting read and write operations associated with the memory in response to the second signal line. ### Claim 28 (depends on 27) The method of claim 27 further comprising: activating a sense amplifier during a read cycle when the voltage of the dummy signal line reaches a first value. ### Claim 29 (depends on 28) The method of claim 28 further comprising: delaying a clock signal in accordance with a control signal; and generating a memory enable signal operative to trigger memory access operations in response to the delayed clock signal.