# US 7,613,054 B2 · SRAM device with enhanced read/write operations

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- Number: US 7,613,054 B2
- Document ID: US7613054B2
- Status: Granted
- Kind: B2
- Application number: 11/924,437
- Filed: 2007-10-25
- Published: 2009-04-30
- Granted: 2009-11-03
- Earliest claimed: 2007-10-25
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Cheng-Hung Lee; Ping-Wei Wang; Ching-Wei Wu; Shu-Hsuan Lin; Feng-Ming Chang; Hung-Jen Liao
- Web page: https://patentgrep.com/patent/US7613054B2

## CPC

- G11C 11/412: using field-effect transistors only
- H10B 10/12: {comprising a MOSFET load element}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

An SRAM device includes: a first group of memory cells connected to a first local bit line and a first local complementary bit line for accessing data nodes thereof; a second group of memory cells connected to a second local bit line and a second local complementary bit line for accessing data nodes thereof; and a global bit line and a global complementary bit line connected to the first and second local bit lines for accessing data nodes of the first and second groups of memory cells, wherein the first local bit line, the first local complementary bit line, the second local bit line, the second local complementary bit line, the global bit line and the global complementary bit line are constructed on a same metallization level in the SRAM device.

## Claims

### Claim 1

A static random access memory (SRAM) device comprising:
a first group of memory cells connected to a first local bit line and a first local complementary bit line for accessing data nodes thereof;
a second group of memory cells connected to a second local bit line and a second local complementary bit line for accessing data nodes thereof; and
a global bit line and a global complementary bit line connected to the first and second local bit lines for accessing data nodes of the first and second groups of memory cells,
wherein the first local bit line, the first local complementary bit line, the second local bit line, the second local complementary bit line, the global bit line and the global complementary bit line are constructed on a same metallization level in the SRAM device.

### Claim 2 (depends on 1)

The SRAM device of claim 1 wherein the metallization level is M2 level.

### Claim 3 (depends on 1)

The SRAM device of claim 1 wherein the global bit line is placed adjacent to the first local bit line for providing a capacitance there between.

### Claim 4 (depends on 3)

The SRAM device of claim 3 wherein the global complementary bit line is placed adjacent to the first local complementary bit line for providing a capacitance there between.

### Claim 5 (depends on 4)

The SRAM device of claim 4 comprising a local power line placed between the first local bit line and the first local complementary bit line.

### Claim 6 (depends on 1)

The SRAM device of claim 1 wherein a signal on the global bit line or the global complementary bit line drops after a signal on the first local bit line or the first local complementary bit line reaches a low state during write operation.

### Claim 7 (depends on 6)

The SRAM device of claim 6 wherein the low state is at a voltage level between 0 and 100 mv.

### Claim 8 (depends on 6)

The SRAM device of claim 6 wherein the signal on the first local bit line or the first local complementary has a negative voltage when the signal on the global bit line or the global complementary bit line drops.

### Claim 9 (depends on 8)

The SRAM device of claim 8 wherein the negative voltage is approximately between −10 and −300 mv.

### Claim 10 (depends on 1)

The SRAM device of claim 1 wherein a signal on the first local bit line or the first local complementary bit line has a same phase as that of a signal on the global bit line or the global complementary bit line.

### Claim 11 (depends on 10)

The SRAM device of claim 10 wherein the signal on the global bit line or the global complementary bit line has a leading edge lagging behind that of the signal on the first local bit line or the first local complementary bit line.

### Claim 12 (depends on 11)

The SRAM device of claim 11 wherein the leading edge of the signal on the global bit line or the global complementary bit line is steeper than that of the signal on the first local bit line or the first local complementary bit line.

### Claim 13

A semiconductor structure comprising:
a first group of memory cells connected to a first local bit line and a first local complementary bit line for accessing data nodes thereof;
a second group of memory cells connected to a second local bit line and a second local complementary bit line for accessing data nodes thereof; and
a global bit line and a global complementary bit line connected to the first and second local bit lines for accessing data nodes of the first and second groups of memory cells,
wherein the first local bit line, the first local complementary bit line, the second local bit line, the second local complementary bit line, the global bit line and the global complementary bit line are constructed on a same metallization level in the semiconductor structure, with the global bit line placed adjacent to the first local bit lines, the global complementary bit line placed adjacent to the first local complementary bit lines.

### Claim 14 (depends on 13)

The semiconductor structure of claim 13 wherein a signal on the global bit line or the global complementary bit line drops after a signal on the first local bit line or the first local complementary bit line reaches a low state during write operation.

### Claim 15 (depends on 14)

The semiconductor structure of claim 14 wherein the low state is at a voltage level between 0 and 100 mv.

### Claim 16 (depends on 15)

The semiconductor structure of claim 15 wherein the signal on the first local bit line or the first local complementary has a negative voltage when the signal on the global bit line or the global complementary bit line drops.

### Claim 17 (depends on 16)

The semiconductor structure of claim 16 wherein the negative voltage is approximately between −10 and −300 mv.

### Claim 18 (depends on 13)

The semiconductor structure of claim 13 wherein a signal on the first local bit line or the first local complementary bit line has a same phase as that of a signal on the global bit line or the global complementary bit line.

### Claim 19 (depends on 18)

The semiconductor structure of claim 18 wherein the signal on the global bit line or the global complementary bit line has a leading edge lagging behind that of the signal on the first local bit line or the first local complementary bit line.

### Claim 20 (depends on 19)

The semiconductor structure of claim 19 wherein the leading edge of the signal on the global bit line or the global complementary bit line is steeper than that of the signal on the first local bit line or the first local complementary bit line.