# US 7,613,046 B2 · Nonvolatile semiconductor memory device carrying out simultaneous programming of memory cells

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- Number: US 7,613,046 B2
- Document ID: US7613046B2
- Status: Granted
- Kind: B2
- Application number: 11/772,271
- Filed: 2007-07-02
- Published: 2007-12-06
- Granted: 2009-11-03
- Earliest claimed: 2000-09-28
- Assignees: Kabushiki Kaisha Toshiba
- Inventors: Noboru Shibata; Tomoharu Tanaka
- Web page: https://patentgrep.com/patent/US7613046B2

## CPC

- G11C 11/5628: {Programming or writing circuits; Data input circuits}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/08: Address circuits; Decoders; Word-line control circuits
- G11C 16/10: Programming or data input circuits
- G11C 16/22: Safety or protection circuits preventing unauthorised or accidental access to memory cells
- G11C 16/3454: {Arrangements for verifying correct programming or for detecting overprogrammed cells}
- G11C 29/832: {with disconnection of faulty elements}
- G11C 16/3436: {Arrangements for verifying correct programming or erasure}
- G11C 29/70: {Masking faults in memories by using spares or by reconfiguring}
- G11C 2211/5621: Multilevel programming verification
- G11C 2211/5641: Multilevel memory having cells with different number of storage levels
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A memory cell array has a first and a second storage area. The first storage area has a memory element selected by an address signal. The second storage area has a memory element selected by a control signal. A control circuit has a fuse element. When the fuse element has been blown, the control circuit inhibits at least one of writing and erasing from being done on the second storage area.

## Claims

### Claim 1

A semiconductor memory device comprising:
a plurality of memory elements to which data is written by a write operation; and
a control circuit, wherein:
in a first write sequence, the control circuit simultaneously stores data in “n” (“n” being a natural number) numbers of said plurality of the memory elements in the write operation and then the control circuit repeats the write operation and a verify operation if any of said “n” numbers of the memory elements are memory elements written insufficiently in the verify operation; and
in a second write sequence, the control circuit simultaneously stores data in “n” (“n” being a natural number) numbers of said plurality of the memory elements in the write operation and then the control circuit repeats the write operation and a verify operation if “k” (“k” being a natural number which is equal to or less than “n”) or greater numbers of said “n” numbers of the memory elements are memory elements written insufficiently in the verify operation.

### Claim 2 (depends on 1)

The semiconductor memory device according to claim 1, wherein the first write sequence is used in a normal write sequence and the second write sequence is used in a test mode.

### Claim 3 (depends on 1)

The semiconductor memory device according to claim 1 further comprising “h” (“h” being a natural number) numbers of memory elements which are selected concurrently with said “n” numbers of the memory elements in which the data are simultaneously stored, said “h” numbers of the memory elements being replaced with the faulty memory elements, wherein “h” is equal to or greater than “k-1” in the second write sequence.