# US 7,613,027 B2 · Semiconductor memory device with dual storage node and fabricating and operating methods thereof

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- Number: US 7,613,027 B2
- Document ID: US7613027B2
- Status: Granted
- Kind: B2
- Application number: 11/907,183
- Filed: 2007-10-10
- Published: 2008-04-17
- Granted: 2009-11-03
- Earliest claimed: 2005-02-14
- Assignees: Samsung Electronics Co., Ltd.
- Inventors: Sang-min Shin; Bon-jae Koo; Yoon-dong Park; Young-soo Park
- Web page: https://patentgrep.com/patent/US7613027B2

## CPC

- G11C 11/22: using ferroelectric elements
- H10B 53/00: Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
- H10B 53/30: characterised by the memory core region
- H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors}
- H10B 63/82: {the switching components having a common active material layer}
- H10N 70/231: {based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect}
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

A semiconductor memory device with a dual storage node structure as well as methods of fabricating and operating such a device are provided. The semiconductor memory device includes a substrate, a first transistor formed on the substrate, a first storage node connected to a source region of the first transistor, a second storage node connected to a drain region of the first transistor, and a plate line commonly contacting the first storage node and the second storage node.

## Claims

### Claim 1

An operating method of a semiconductor memory device, the semiconductor memory device including a substrate, a first transistor formed on the substrate, a first storage node connected to a source region of the first transistor, a second storage node connected to a drain region of the first transistor, and a plate line commonly contacting the first storage node and the second storage node, the operating method comprising:
floating the drain region while maintaining the first transistor turned off; and
generating a first electric potential difference between the source region of the first transistor and the plate line.

### Claim 2 (depends on 1)

The operating method of claim 1, further comprising, after the generating of the first electric potential difference: floating the source region while maintaining the first transistor turned off; and
generating a second electric potential difference between the drain region and the plate line.

### Claim 3 (depends on 2)

The operating method of claim 2, wherein the second electric potential difference is generated by supplying a write voltage to the drain region and approximately 0 V to the plate line.

### Claim 4 (depends on 2)

The operating method of claim 2, wherein the second electric potential difference is generated by supplying approximately 0 V to the drain region and a write voltage to the plate line.

### Claim 5 (depends on 1)

The operating method of claim 1, wherein the first electric potential difference is generated by supplying a write voltage to the source region and approximately 0 V to the plate line.

### Claim 6 (depends on 1)

The operating method of claim 1, wherein the first electric potential difference is generated by supplying approximately 0 V to the source region and a write voltage to the plate line.

### Claim 7 (depends on 1)

The method of claim 1, wherein the first and the second storage nodes are one of capacitors and ferroelectric capacitors.

### Claim 8 (depends on 1)

The operating method of claim 1, wherein the first and the second storage nodes are one of PRAM storage nodes and RRAM storage nodes.

### Claim 9 (depends on 8)

The operating method of claim 8, wherein the first and second storage nodes include a material having a minimum resistance higher than the resistance of the first transistor when turned on.

### Claim 10 (depends on 1)

The operating method of claim 1, further comprising:
a second transistor sharing the source region and the first storage node; and
a third transistor sharing the drain region and the second storage node.