# US 7,613,025 B2 · Dram cell design with folded digitline architecture and angled active areas > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,613,025 B2 - Document ID: US7613025B2 - Status: Granted - Kind: B2 - Application number: 12/022,451 - Filed: 2008-01-30 - Published: 2008-06-12 - Granted: 2009-11-03 - Earliest claimed: 2006-03-15 - Assignees: Micron Technology, Inc. - Inventors: Fei Wang; Anton P. Eppich - Web page: https://patentgrep.com/patent/US7613025B2 ## CPC - G11C 11/4097: Bit-line organisation, e.g. bit-line layout, folded bit lines - G11C 7/02: with means for avoiding parasitic signals - G11C 7/18: Bit line organisation; Bit line lay-out - H10B 12/48: {Data lines or contacts therefor} - H10D 89/10: Integrated device layouts - G11C: STATIC STORES (semiconductor memory devices H10B) - H10B: ELECTRONIC MEMORY DEVICES - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract The present invention is generally directed to a DRAM cell design with folded digitline sense amplifier. In one illustrative embodiment, a memory array having a plurality of memory cells having an effective size of 6 F2 is disclosed which has a plurality of dual bit active areas, each of the active areas having a substantially longitudinal axis, and a plurality of digitlines on a 3 F-pitch arranged in a folded digitline architecture, wherein the active areas are positioned such that the longitudinal axis of the active areas is oriented at an angle with respect to a centerline of the digitlines. ## Claims ### Claim 1 A DRAM device comprised of a plurality of memory cells having an effective size of 6 F2, comprising: a plurality of dual bit active areas, each of said active areas having a substantially longitudinal axis; and a plurality of digitlines arranged in a folded digitline architecture, wherein said digitlines have a 3 F pitch and 2 F space between adjacent digit lines, and wherein said active areas are positioned such that the longitudinal axis of said active areas is oriented at an angle with respect to a centerline of said digitlines. ### Claim 2 (depends on 1) The DRAM device of claim 1, wherein the digitlines have a width of F. ### Claim 3 (depends on 1) The DRAM device of claim 1, further comprising a plurality of word lines having a pitch different from that of the digitlines. ### Claim 4 (depends on 3) The DRAM device of claim 3, wherein the pitch of the word lines is F. ### Claim 5 (depends on 4) The DRAM device of claim 4, further comprising a plurality of word lines having a width less than F. ### Claim 6 (depends on 5) The DRAM device of claim 5, wherein the word lines have a width equal to about 0.5 F. ### Claim 7 (depends on 1) The DRAM device of claim 1, wherein said angle ranges from approximately 20-80 degrees. ### Claim 8 (depends on 1) The DRAM device of claim 1, wherein said angle is approximately 49 degrees. ### Claim 9 (depends on 1) The DRAM device of claim 1, wherein said angle is approximately 49.58 degrees. ### Claim 10 (depends on 1) The DRAM device of claim 1, further comprising a plurality of buried word line structures that extend through said active areas. ### Claim 11 (depends on 1) The DRAM device of claim 1, wherein said active areas have rounded ends. ### Claim 12 (depends on 1) The DRAM device of claim 1, wherein said active areas have non-rounded ends. ### Claim 13 (depends on 1) The DRAM device of claim 1, wherein portions of each of said active areas extend into areas occupied by adjacent memory cells. ### Claim 14 (depends on 1) The DRAM device of claim 1, wherein longitudinally opposing portions of each of said active areas extend into areas occupied by adjacent memory cells, the longitudinally opposing portions being unequal in area. ### Claim 15 (depends on 1) The DRAM device of claim 1, wherein the plurality of digitlines comprise a plurality of pairs of digitlines and reference digitlines arranged in the folded digitline architecture such that each dual bit active area contacts either a digitline or a reference digitline, wherein said digitlines and reference digitlines have a 3 F pitch and wherein active areas contacting digitlines are positioned such that the longitudinal axis of said active areas is oriented at a positive value of an angle with respect to a centerline of said digitlines and active areas contacting reference digitlines are positioned such that the longitudinal axis of said active areas is oriented at a negative value of the angle with respect to a centerline of said reference digitlines. ### Claim 16 (depends on 1) The DRAM device of claim 1, comprising a digitline contact area within each of the active areas, said digitline contact area being rectangular. ### Claim 17 (depends on 16) The DRAM device of claim 16, comprising a capacitor contact area within each of the active areas, said capacitor contact area not being rectangular. ### Claim 18 (depends on 1) The DRAM device of claim 1, comprising a capacitor contact area within each of the active areas, said capacitor contact area not being rectangular. ### Claim 19 (depends on 1) The DRAM device of claim 1, comprising a capacitor contact area within each of the active areas, said capacitor contact area having a curved end. ### Claim 20 (depends on 1) The DRAM device of claim 1, comprising an elongated capacitor contact area within each of the active areas, said elongated capacitor contact area having opposing ends, one of the ends having a curved portion, another of the ends being void of any curved portion. ### Claim 21 (depends on 1) The DRAM device of claim 1, further comprising a plurality of word lines, space between adjacent of the word lines being 0.5 F. ### Claim 22 A DRAM device comprised of a plurality of memory cells, comprising: a plurality of dual bit active areas, each of said active areas having a substantially longitudinal axis; a plurality of digitlines arranged in a folded digitline architecture, said active areas being positioned such that the longitudinal axis of said active areas is oriented at an angle with respect to a centerline of said digitlines; and a plurality of word lines having a pitch which is one third that of the digitlines. ### Claim 23 (depends on 21) The DRAM device of claim 21, wherein the digitline pitch is 3 F and the word line pitch is 1 F. ### Claim 24 (depends on 21) The DRAM device of claim 21, wherein the memory cells have an effective size of 6 F2. ### Claim 25 A DRAM device comprised of a plurality of memory cells, comprising: a plurality of dual bit active areas, each of said active areas having a substantially longitudinal axis; a plurality of digitlines arranged in a folded digitline architecture, said active areas being positioned such that the longitudinal axis of said active areas is oriented at an angle with respect to a centerline of said digitlines; and a plurality of word lines, space between adjacent of the digitlines being four times space between adjacent of the word lines. ### Claim 26 (depends on 25) The DRAM device of claim 25, wherein space between adjacent of the digitlines is greater than F. ### Claim 27 (depends on 25) The DRAM device of claim 25, wherein space between adjacent of the word lines is less than F. ### Claim 28 (depends on 27) The DRAM device of claim 27, wherein space between adjacent of the word lines is 0.5 F. ### Claim 29 (depends on 27) The DRAM device of claim 27, wherein space between adjacent of the digitlines is greater than F. ### Claim 30 A DRAM device comprised of a plurality of memory cells, comprising: a plurality of dual bit active areas, each of said active areas having a substantially longitudinal axis; a plurality of digitlines arranged in a folded digitline architecture, said active areas being positioned such that the longitudinal axis of said active areas is oriented at an angle with respect to a centerline of said digitlines; and an elongated capacitor contact area within each of the active areas, said elongated capacitor contact area having opposing ends, one of the ends having a curved portion, another of the ends being void of any curved portion.