# US 7,613,022 B2 · Semiconductor memory device and method of forming the same

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- Number: US 7,613,022 B2
- Document ID: US7613022B2
- Status: Granted
- Kind: B2
- Application number: 11/819,174
- Filed: 2007-06-26
- Published: 2007-12-27
- Granted: 2009-11-03
- Earliest claimed: 2006-06-26
- Assignees: Samsung Electronics Co., Ltd.
- Inventors: Hiroki Murakami
- Web page: https://patentgrep.com/patent/US7613022B2

## CPC

- H10W 20/495: {Capacitive arrangements or effects of, or between wiring layers}
- H10B 99/00: Subject matter not provided for in other groups of this subclass
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

Example embodiments provide a semiconductor memory device and method of forming a semiconductor memory device that may equalize load due to a coupling capacitance between a line and a component signal when the line intersects the component signal in a memory cell array. A line may intersect a memory cell region between a transmitting point (A) and a receiving point (B) of a signal. A line between the transmitting point (A) and the receiving point (B) may be bent at two portions of each of bit lines. Because areas where the line and the bit lines extend parallel to each other may be equal in dimension at each bit line, coupling capacitances between the line and the bit lines may be equalized. The read characteristic may not be affected by the coupling capacitances.

## Claims

### Claim 1

A semiconductor memory device, comprising:
a memory cell array defining a memory cell region, including a plurality of word lines, a plurality of bit lines, and a plurality of memory cells arranged at intersections of the plurality of word lines and the plurality of bit lines in a matrix form; and
a line, crossing the memory cell region, to connect first and second peripheral circuits, disposed in a peripheral region, to each other, wherein a coupling capacitance between the line and each of the plurality of bit lines is equalized; wherein
the line includes a plurality of bent portions at each of the plurality of bit lines.

### Claim 2 (depends on 1)

The semiconductor memory device of claim 1, wherein the line includes areas where the line and the plurality of bit lines extend parallel to each other are equal in dimension at each bit line.

### Claim 3 (depends on 2)

The semiconductor memory device of claim 2, wherein a total number of the plurality of bent portions is greater than an integer multiple of a total number of the plurality of bit lines.

### Claim 4 (depends on 1)

The semiconductor memory device of claim 1, wherein the line includes areas where the line and the plurality of bit lines overlap each other are equal in dimension at each bit line.

### Claim 5 (depends on 4)

The semiconductor memory device of claim 4, wherein a total number of the plurality of bent portions is greater than an integer multiple of a total number of the plurality of bit lines.

### Claim 6 (depends on 5)

The semiconductor memory device of claim 5, wherein the line extends perpendicular to each of the plurality of bit lines.

### Claim 7 (depends on 1)

The semiconductor memory device of claim 1, wherein the line extends linearly between the first and second peripheral circuits in the memory cell region.

### Claim 8

A method of forming a semiconductor memory device, comprising:
providing a memory cell array defining a memory cell region, including a plurality of word lines, a plurality of bit lines, and a plurality of memory cells arranged at intersections of the plurality of word lines and the plurality of bit lines in a matrix form; and
forming a line, crossing the memory cell region, to connect first and second peripheral circuits, disposed in a peripheral region, to each other, wherein a coupling capacitance between the line and each of the plurality of bit lines equalized; is wherein
forming the line includes forming a plurality of bent portions at each of the plurality of bit lines.

### Claim 9 (depends on 8)

The method of claim 8, wherein forming the line includes areas where the line and the plurality of bit lines extend parallel to each other are equal in dimension at each bit line.

### Claim 10 (depends on 9)

The method of claim 9, wherein a total number of the plurality of bent portions is greater than an integer multiple of a total number of the plurality of bit lines.

### Claim 11 (depends on 8)

The method of claim 8, wherein forming the line includes areas where the line and the plurality of bit lines overlap each other are equal in dimension at each bit line.

### Claim 12 (depends on 11)

The method of claim 11, wherein a total number of the plurality of bent portions is greater than an integer multiple of a total number of the plurality of bit lines.

### Claim 13 (depends on 8)

The method of claim 8, wherein the line extends linearly between the first and second peripheral circuits in the memory cell region.

### Claim 14 (depends on 13)

The method of claim 13, wherein the line extends perpendicular to each of the plurality of bit lines.