# US 7,612,984 B2 · Layout for capacitor pair with high capacitance matching > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,612,984 B2 - Document ID: US7612984B2 - Status: Granted - Kind: B2 - Application number: 11/591,643 - Filed: 2006-11-01 - Published: 2008-05-01 - Granted: 2009-11-03 - Earliest claimed: 2006-11-01 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Chia-Yi Chen; Chung-Long Chang; Chih-Ping Chao - Web page: https://patentgrep.com/patent/US7612984B2 ## CPC - H10D 84/212: {of only capacitors} - H10W 20/496: {Capacitor integral with wiring layers} - H01G 4/38: Multiple capacitors, i.e. structural combinations of fixed capacitors - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H01G: CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE (selection of specified materials as dielectric H01B3/00; capacitors having potential barriers H10D1/62, H10K10/10) ## Abstract An integrated circuit device includes a capacitor array, which includes unit capacitors arranged in rows and columns, wherein each unit capacitor is formed of two electrically insulated capacitor plates. The unit capacitors include at least one first unit capacitor in each row and in each column of the capacitor array; the at least one first unit capacitor being interconnected, wherein each row of the capacitor array comprises a same number of the at least one first unit capacitors as other rows and columns have, and wherein each column of the capacitor array comprises a same number of the at least one first unit capacitors as other rows and columns have. The unit capacitors further include at least one second unit capacitor in each row and in each column of the capacitor array, wherein the at least one second unit is interconnected and evenly distributed throughout the array. ## Claims ### Claim 1 An integrated circuit device comprising: a capacitor array comprising unit capacitors arranged in rows and columns, wherein each unit capacitor is formed of two electrically insulated capacitor plates; at least one first unit capacitor in each row and in each column of the capacitor array, the at least one first unit capacitor being interconnected, wherein each row of the capacitor array comprises a same number of the at least one first unit capacitors as other rows and columns have, and wherein each column of the capacitor array comprises a same number of the at least one first unit capacitors as other rows and columns have; and more than one second unit capacitor in each row and in each column of the capacitor array, the more than one second unit capacitor being interconnected, wherein each row of the capacitor array comprises a same number of the more than one second unit capacitors as other rows and columns have, and wherein each column of the capacitor array comprises a same number of the more than one second unit capacitors as other rows and columns have. ### Claim 2 (depends on 1) The integrated circuit device in claim 1, wherein, in each row and in each column, there is only one of the at least one first unit capacitor. ### Claim 3 (depends on 1) The integrated circuit device in claim 1, wherein the at least one first unit capacitor and the more than one second unit capacitor share a common node. ### Claim 4 (depends on 1) The integrated circuit device in claim 1, wherein the at least one first unit capacitor and the more than one second unit capacitor have no common node. ### Claim 5 (depends on 1) The integrated circuit device in claim 1, wherein the capacitor array is formed in one metallization layer, and wherein each of the at least one first unit capacitors and the more than one second unit capacitors are formed between sidewalls of metal fingers. ### Claim 6 An integrated circuit device comprising: a capacitor array comprising unit capacitors arranged in rows and columns, wherein each unit capacitor is formed of two electrically insulated capacitor plates; at least one first unit capacitor in each row and in each column of the capacitor array, the at least one first unit capacitor being interconnected, wherein each row of the capacitor array comprises a same number of the at least one first unit capacitors as other rows and columns have, and wherein each column of the capacitor array comprises a same number of the at least one first unit capacitors as other rows and columns have; at least one second unit capacitor in each row and in each column of the capacitor array, the at least one second unit capacitor being interconnected, wherein each row of the capacitor array comprises a same number of the at least one second unit capacitors as other rows and columns have, and wherein each column of the capacitor array comprises a same number of the at least one second unit capacitors as other rows and columns have; and at least one third unit capacitor in each row and in each column of the capacitor array, the at least one third unit capacitor being interconnected, wherein each row of the capacitor array comprises a same number of the at least one third unit capacitors as other rows and columns have, and wherein each column of the capacitor array comprises a same number of the at least one third unit capacitors as other rows and columns have. ### Claim 7 (depends on 6) The integrated circuit device in claim 6, wherein the at least one first unit capacitor and the at least one second unit capacitor form a first capacitor pair, the at least one second unit capacitor and the at least one third unit capacitor form a second capacitor pair, and the at least one third unit capacitor and the at least one first unit capacitor form a third capacitor pair. ### Claim 8 An integrated circuit device comprising: a capacitor array comprising unit capacitors arranged in rows and columns, wherein each unit capacitor is formed of two electrically insulated capacitor plates; at least one first unit capacitor in each row and in each column of the capacitor array, the at least one first unit capacitor being interconnected, wherein each row of the capacitor array comprises a same number of the at least one first unit capacitors as other rows and columns have, and wherein each column of the capacitor array comprises a same number of the at least one first unit capacitors as other rows and columns have; at least one second unit capacitor in each row and in each column of the capacitor array, the at least one second unit capacitor being interconnected, wherein each row of the capacitor array comprises a same number of the at least one second unit capacitors as other rows and columns have, and wherein each column of the capacitor array comprises a same number of the at least one second unit capacitors as other rows and columns have; at least one third unit capacitor connected to the at least one first unit capacitor; and at least one fourth unit capacitor connected to the at least one second unit capacitor, wherein the at least one third unit capacitor and the at least one fourth unit capacitor form an additional array, and wherein the at least one first unit capacitor is parallel connected to the at least one third unit capacitor, and the at least one second unit capacitor is parallel connected to the at least one fourth unit capacitor. ### Claim 9 (depends on 8) The integrated circuit device in claim 8, wherein the array and the additional array are in a same metallization layer. ### Claim 10 (depends on 8) The integrated circuit device in claim 8, wherein the array and the additional array are in different metallization layers. ### Claim 11 (depends on 8) The integrated circuit device in claim 8, wherein, in a same row or in a same column, the at least one first unit capacitor and the at least one second unit capacitor are substantially evenly distributed. ### Claim 12 An integrated circuit device comprising: a common node comprising a first conductive bus and a plurality of first fingers connected to the first conductive bus; a plurality of second fingers, each being between and electrically insulated from two of the first fingers; a second conductive bus interconnecting the plurality of second fingers; a plurality of third fingers, each being between and electrically insulated from two of the first fingers; a third conductive bus interconnecting the plurality of third fingers, wherein the plurality of first fingers, the plurality of second fingers, and the plurality of third fingers are metal lines in a metallization layer; and wherein the plurality of second fingers and the plurality of third fingers form an array with rows and columns, wherein, in each row and in each column, a number of the second fingers is equal to a number of the second fingers in other rows and columns, and wherein, in each row and in each column, a number of the third fingers is equal to a number of the third fingers in other rows and columns. ### Claim 13 (depends on 12) The integrated circuit device of claim 12, wherein at least a portion of the second and the third conductive buses are formed in a different metallization layer than the first and the second plurality of fingers. ### Claim 14 (depends on 12) The integrated circuit device of claim 12, wherein there is only one of the second fingers in each row and in each column. ### Claim 15 (depends on 14) The integrated circuit device of claim 14, wherein there is more than one of the third fingers in each row and in each column. ### Claim 16 (depends on 12) The integrated circuit device of claim 12 further comprising a plurality of fourth fingers, wherein each of the fourth fingers is between and electrically insulated from two of the first fingers, and wherein, in each row and in each column, a number of the fourth fingers is equal to a number of the fourth fingers in other rows and columns. ### Claim 17 A capacitor pair comprising: a common node comprising a first conductive bus and a plurality of first fingers connected to the first conductive bus; a number of M*(M+N) second fingers, each second finger being between and electrically insulated from two of the first fingers, wherein M and N are non-zero integers; a second conductive bus interconnecting the second fingers; a number of N*(M+N) third fingers, each being between and electrically insulated from two of the first fingers; a third conductive bus interconnecting the third fingers, wherein the first fingers, the second fingers, and the third fingers are metal lines in a metallization layer; and wherein the second fingers and the third fingers form an array with M+N rows and M+N columns, wherein, in each row and in each column, there are M second fingers and N third fingers. ### Claim 18 (depends on 17) The capacitor pair of claim 17, wherein M is one and N is greater than one. ### Claim 19 (depends on 17) The capacitor pair of claim 17, wherein a centroid of the first fingers and a centroid of the second fingers substantially overlap.