# US 7,612,815 B2 · Optical sensor

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- Number: US 7,612,815 B2
- Document ID: US7612815B2
- Status: Granted
- Kind: B2
- Application number: 10/539,068
- Filed: 2003-12-16
- Published: 2006-10-12
- Granted: 2009-11-03
- Earliest claimed: 2002-12-16
- Assignees: Hamamatsu Photonics K.K.
- Inventors: Yasuhiro Suzuki; Seiichiro Mizuno
- Web page: https://patentgrep.com/patent/US7612815B2

## CPC

- H04N 25/00: Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N 25/78: Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
- H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION

## Abstract

The present invention aims at providing a photodetector which can secure both a good S/N ratio and a high speed. With a photodetector 1, (K×M×N) photodiodes PDk,m,n are arranged in M rows and (K×N) columns in a photodetection unit 10, and processes (electric charge accumulation, CDS, filtering, and A/D conversion) regarding each of the (K×N) photodiodes PDk,m,n (k=1 to K, n=1 to N) of each row are carried out successively at each time T. Meanwhile, each of an electric charge accumulation operation in an integrating circuit 20m,n, a CDS operation in a CDS circuit 30m,n, a filtering operation in a filter circuit 40m,n, and an A/D conversion operation in an A/D converter 50m,n is carried out at each time (N×T).

## Claims

### Claim 1

A photodetector comprising:
(K×M×N) photodiodes PDk,m,n (K being an integer of no less than 2; k being integers of no less than 1 and no more than K; M being an integer of no less than 1; m being integers of no less than 1 and no more than M; N being an integer of no less than 2; and n being integers of no less than 1 and no more than N), each generating an electric charge by an amount corresponding to an intensity of light incident thereon;
(M×N) integrating circuits, one of each being provided in correspondence to K photodiodes PDk,m,n (k=1 to K) among the (K×M×N) photodiodes PDk,m,n and each successively inputting and accumulating the electric charges generated at the K photodiodes PDk,m,n (k=1 to K) and outputting a voltage that is in accordance with the amount of the accumulated electric charges; and
(M×N) filter circuits, one of each being provided in correspondence to each of the (M×N) integrating circuits and each reducing the thermal noise component contained in the voltage output from the corresponding integrating circuit and outputting the voltage after reduction of the thermal noise component,
wherein the (K×M×N) photodiodes PDk,m,n are arranged in M rows and (K×N) columns either two-dimensionally (when M=2) or one-dimensionally (when M=1), with each photodiode PDk,m,n being positioned at the position of the m-th row and (n+(k−1)N)-th column,
switches SWk,m,n are provided in a one-to-one correspondence with respect to photodiodes PDk,m,n and are arranged between the photodiodes PDk,m,n and signal lines SLm,n,
each set of K photodiodes PDk,m,n (k=1 to K) is connected via the corresponding switches SWk,m,n to a signal line SLm,n,
each signal line SLm,n is connected to an input end of an integrating circuit, and
switches SWk,m,n on the same row are connected to the same control line CLk,n and the opening/closing of each row of switches SWk,m,n is controlled together by a control signal that is transmitted via the control line CLk,n.

### Claim 2 (depends on 1)

The photodetector according to claim 1, further comprising CDS circuits, each being arranged between said integrating circuit and said filter circuit, inputting the voltage output from the integrating circuit, and outputting a voltage expressing the fluctuation of the input voltage over a fixed time.

### Claim 3 (depends on 1)

The photodetector according to claim 1, further comprising A/D converters, each inputting the voltage output from said filter circuit, performing A/D conversion on this voltage, and outputting a digital value that is in accordance with this voltage.