# US 7,612,754 B2 · Shift register units, display panels utilizing the same, and methods for improving current leakage thereof

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- Number: US 7,612,754 B2
- Document ID: US7612754B2
- Status: Granted
- Kind: B2
- Application number: 11/231,224
- Filed: 2005-09-20
- Published: 2006-08-24
- Granted: 2009-11-03
- Earliest claimed: 2005-02-21
- Assignees: Au Optronics Corporation
- Inventors: Chung-Hong Kuo; Jian-Shen Yu
- Web page: https://patentgrep.com/patent/US7612754B2

## CPC

- G09G 3/3677: {suitable for active matrices only}
- G11C 19/28: using semiconductor elements (G11C19/14, G11C19/36 take precedence)
- G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A shift register comprising at least one shift register unit. The shift register unit comprises an input unit, at least one first TFT, and at least one second TFT. The input unit receives an input signal from the input terminal and outputs a switching control signal in accordance with a first clock signal. The gate of the first TFT is for receiving the switching control signal, the drain of the first TFT is for receiving a second clock signal, and the source of the first TFT is coupled to the output terminal. The gate and drain of the second TFT are coupled to the output terminal, and the source of the second TFT is coupled to the input unit.

## Claims

### Claim 1

A shift register unit having an input terminal and an output terminal, comprising:
an input unit, in accordance with a first clock signal, configured to receive an input signal from the input terminal and output a switching control signal;
at least one first transistor coupled to the input unit, wherein the gate of the first transistor is configured to receive the switching control signal, the drain of the first transistor is configured to receive a second clock signal, and the source of the first transistor is coupled to the output terminal; and at least one second transistor, wherein the gate and the drain of the second transistor are coupled to the output terminal, and the source of the second transistor is coupled to the input unit.

### Claim 2 (depends on 1)

The shift register unit as claimed in claim 1, wherein the first and second clock signals have reverse phases.

### Claim 3 (depends on 1)

The shift register unit as claimed in claim 1, further comprising a third transistor, wherein the gate of the third transistor is configured to receive a first control signal, the drain of the third transistor is coupled to the output terminal, and the source of the third transistor is coupled to ground.

### Claim 4 (depends on 1)

The shift register unit as claimed in claim 1, wherein the input unit comprises:
a fourth transistor, wherein the gate of the fourth transistor is configured to receive the first clock signal and the drain of the fourth transistor is configured to receive the input signal; and
a fifth transistor, wherein the gate of the fifth transistor is configured to receive the first clock signal, the drain of the fifth transistor is coupled to the source of the fourth transistor, and the source of the fifth transistor is coupled to the gate of the first transistor.

### Claim 5 (depends on 4)

The shift register unit as claimed in claim 4, wherein the fourth and fifth transistors are P-type thin film transistors, the first transistor is an N-type thin film transistor, and the first and second clock signals have same phases.

### Claim 6 (depends on 4)

The shift register unit as claimed in claim 4, wherein the source of the second transistor is coupled to the source of the fourth transistor and the drain of the fifth transistor.

### Claim 7 (depends on 6)

The shift register unit as claimed in claim 6, further comprising a third transistor, wherein the gate of the third transistor is configured to receive a first control signal, the drain of the third transistor is coupled to the output terminal, and the source of the third transistor is coupled to ground.

### Claim 8 (depends on 1)

The shift register unit as claimed in claim 1, wherein the input unit comprises:
a fourth transistor, wherein the gate and the drain of the fourth transistor are configured to receive the input signal;
a fifth transistor, wherein the gate of the fifth transistor is configured to receive the first clock signal, the drain of the fifth transistor is coupled to the source of the fourth transistor, and the source of the fifth transistor is coupled to the gate of the first transistor;
a sixth transistor, wherein the gate of the sixth transistor is configured to receive a second control signal, the drain of the sixth transistor is coupled to the gate of the first transistor, and the source of the sixth transistor is coupled to the source of the second transistor; and
a seventh transistor, wherein the gate of the seventh transistor is configured to receive a second control signal, the drain of the seventh transistor is coupled to the source of the sixth transistor, and the source of the seventh transistor is coupled to ground.

### Claim 9 (depends on 1)

A display panel comprising a shift register unit of claim 1.