# US 7,612,645 B2 · Integrated inductor

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- Number: US 7,612,645 B2
- Document ID: US7612645B2
- Status: Granted
- Kind: B2
- Application number: 11/548,687
- Filed: 2006-10-11
- Published: 2007-06-07
- Granted: 2009-11-03
- Earliest claimed: 2005-10-12
- Assignees: Realtek Semiconductor Corp.
- Inventors: Ta-Hsun Yeh; Yuh-Sheng Jean
- Web page: https://patentgrep.com/patent/US7612645B2

## CPC

- H01F 17/0006: {Printed inductances (printed coils for dynamo-electric machines H02K3/26; printed circuits H05K)}
- H10W 20/497: {Inductive arrangements or effects of, or between, wiring layers}
- H01F 27/34: Special means for preventing or reducing unwanted electric or magnetic effects, e.g. no-load losses, reactive currents, harmonics, oscillations, leakage fields
- H01F: MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

An integrated inductor formed on a substrate comprises a metal layer pattern, a via layer pattern overlapping and electrically connected to the metal layer, and a redistribution layer pattern overlapping and electrically connected to the via layer. The metal layer pattern, the via layer pattern, and the redistribution layer pattern are a coil pattern.

## Claims

### Claim 1

An inductor formed in an integrated circuit, the inductor comprising:
a metal layer pattern;
a redistribution layer pattern formed above the metal layer pattern; the redistribution layer pattern residing in a redistribution layer comprising a part of at least a bond pad structure; and
a via layer pattern formed between the metal layer pattern and the redistribution layer pattern, the via layer pattern electrically conductively contacting the metal layer pattern and the redistribution layer pattern;
wherein the metal layer pattern, the via layer pattern and the redistribution layer pattern substantially overlap at different layers in a coil pattern.

### Claim 2 (depends on 1)

The inductor of claim 1, wherein the metal layer pattern is a top metal layer.

### Claim 3 (depends on 1)

The inductor of claim 1, wherein the metal layer pattern is a coil pattern, and the redistribution layer pattern is a coil pattern, the metal layer pattern substantially overlapping the redistribution layer pattern.

### Claim 4 (depends on 3)

The inductor of claim 3, wherein the via layer pattern is a set of plural metal islands scattered between the metal layer pattern and the redistribution layer.

### Claim 5 (depends on 1)

The inductor of claim 1, wherein the metal layer pattern comprises copper.

### Claim 6 (depends on 5)

The inductor of claim 5, wherein the redistribution layer pattern and the via layer pattern comprise aluminum.

### Claim 7 (depends on 1)

The inductor of claim 1, wherein the metal layer pattern, the redistribution layer pattern, and the via layer pattern provide a substantial inductance.

### Claim 8 (depends on 1)

The inductor of claim 1, wherein the inductor is fabricated with a 0.13 μm process or a more advanced process.

### Claim 9 (depends on 8)

The inductor of claim 8, wherein the metal layer has a thickness of approximately 10 k Å or less, the redistribution layer has a thickness of approximately 13 k Å or less, and the via layer has a thickness of approximately 12 k Å or less.

### Claim 10

An inductor formed in an integrated circuit, the inductor comprising:
a substrate;
a first metal pattern formed above the substrate; and
a second metal pattern formed above the first metal pattern and electrically conductively contacting the first metal pattern, wherein second metal pattern includes a via layer pattern and a redistribution layer pattern, the redistribution layer pattern residing in a redistribution layer comprising a part of at least a bond pad structure;
wherein the inductor provides a substantial inductance, and the first metal pattern and the second metal pattern are made of different metal materials.

### Claim 11 (depends on 10)

The inductor of claim 10, wherein the first metal pattern comprises copper.

### Claim 12 (depends on 11)

The inductor of claim 11, wherein the second metal pattern comprises aluminum.

### Claim 13 (depends on 10)

The inductor of claim 10, wherein the first metal pattern is a coil pattern, and the second metal pattern is a coil pattern, the first metal pattern substantially overlapping the second metal pattern.

### Claim 14 (depends on 10)

The inductor of claim 10, wherein the inductor is fabricated with a CMOS standard process.

### Claim 15 (depends on 14)

The inductor of claim 14, wherein the first metal pattern includes a top metal layer formed by a CMOS standard process.

### Claim 16 (depends on 15)

The inductor of claim 15, wherein the CMOS standard process is a 0.13 μm process or a more advanced process.

### Claim 17 (depends on 10)

The inductor of claim 10, wherein the first metal pattern has a thickness of approximately 10 k Å or less, the redistribution layer has a thickness of approximately 13 k Å or less, and the via layer has a thickness of approximately 12 k Å or less.

### Claim 18

A semiconductor element formed in an integrated circuit comprising a metal layer and at least one bond pad, the semiconductor element comprising:
a metal layer pattern formed in the metal layer;
a redistribution layer pattern formed above the metal layer pattern, the redistribution layer pattern residing in a redistribution layer comprising at least one part of the at least a bond pad; and
an interconnect layer pattern formed between the metal layer and the redistribution layer, the interconnect layer electrically conductively contacting the metal layer pattern and the redistribution layer pattern.

### Claim 19 (depends on 18)

The semiconductor element of claim 18 comprising an inductor.

### Claim 20 (depends on 18)

The semiconductor element of claim 18, wherein the metal layer pattern and the redistribution layer pattern substantially overlap at different layers.

### Claim 21 (depends on 18)

The semiconductor element of claim 18, wherein the metal layer is a top metal layer.

### Claim 22 (depends on 18)

The semiconductor element of claim 18, wherein the metal layer pattern, the redistribution layer pattern, and the interconnect layer pattern provide a substantial inductance.

### Claim 23 (depends on 18)

The semiconductor element of claim 18, wherein the redistribution layer pattern is a coil pattern.

### Claim 24 (depends on 18)

The semiconductor element of claim 18, wherein the redistribution layer pattern comprises copper.

### Claim 25 (depends on 18)

The semiconductor element of claim 18, wherein the redistribution layer pattern comprises aluminum.

### Claim 26 (depends on 18)

The semiconductor element of claim 18, wherein the metal layer formed by a CMOS standard process.

### Claim 27 (depends on 18)

The semiconductor element of claim 18, wherein the semiconductor element is fabricated with a 0.13 μm process or a more advanced process.

### Claim 28 (depends on 18)

The semiconductor element of claim 18, wherein the interconnect layer pattern comprises a via layer pattern.

### Claim 29

A semiconductor element formed in an integrated circuit comprising a metal layer and at least one bond pad, the semiconductor element comprising:
a first metal pattern formed in the metal layer; and
a second metal pattern formed above the metal layer and electrically conductively contacting the first metal pattern, wherein the second metal pattern includes an interconnect pattern residing in an interconnect layer comprising a first part of the at least one bond pad.

### Claim 30 (depends on 29)

The semiconductor element of claim 29, wherein the second metal pattern includes a redistribution pattern residing in a redistribution layer comprising a second part of the at least one bond pad.

### Claim 31 (depends on 29)

The semiconductor element of claim 29, wherein the redistribution layer pattern comprises copper.

### Claim 32 (depends on 29)

The semiconductor element of claim 29, wherein the redistribution layer pattern comprises aluminum.

### Claim 33 (depends on 29)

The semiconductor element of claim 29, wherein the first metal pattern substantially overlapping the second metal pattern.

### Claim 34 (depends on 29)

The semiconductor element of claim 29, wherein the semiconductor element is fabricated with a CMOS standard process.

### Claim 35 (depends on 29)

The semiconductor element of claim 29, wherein the metal layer comprises a top metal layer.

### Claim 36 (depends on 29)

The semiconductor element of claim 29, wherein the CMOS standard process is a 0.13 μm process or a more advanced process.

### Claim 37 (depends on 29)

The semiconductor element of claim 29 comprising an inductor.