# US 7,612,620 B2 · System and method for conditioning differential clock signals and integrated circuit load board using same

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 7,612,620 B2
- Document ID: US7612620B2
- Status: Granted
- Kind: B2
- Application number: 11/824,075
- Filed: 2007-06-29
- Published: 2009-01-01
- Granted: 2009-11-03
- Earliest claimed: 2007-06-29
- Assignees: Micron Technology, Inc.
- Inventors: Greg Rausch; Robert Rabe; Curtis Schnarr
- Web page: https://patentgrep.com/patent/US7612620B2

## CPC

- H03K 5/1565: {the output pulses having a constant duty cycle}
- G11C 29/02: Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C 29/023: {in clock generator or timing circuitry}
- G11C 29/028: {with adaption or trimming of parameters}
- H03K 5/15013: {with more than two outputs}
- G11C 11/401: forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C 2207/2254: Calibration
- H03K 2005/00052: {by mixing the outputs of fixed delayed signals with each other or with the input signal}
- H03K 2005/00286: {Phase shifter, i.e. the delay between the output and input pulse is dependent on the frequency, and such that a phase difference is obtained independent of the frequency}
- H03L 7/06: using a reference signal applied to a frequency- or phase-locked loop
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)

## Abstract

A system and method of conditioning differential clock signals iteratively adjusts the duty cycles and phases of the clock signals. The duty cycles of the clock signals are adjusted by comparing respective voltage corresponding to the duty cycles of respective clock signals in each of the differential pairs. The result of the comparison is used to adjust the duty cycles of the clock signal until the magnitudes of the voltages are substantially equal. The phases of the clock signals are adjusted by selecting two sets of two clock signals each that are assigned relative phases that differ from each other by the same amount. The selected sets of clock signals are processed so that the duty cycles of resulting signals correspond to the phases of the clock signals. The duty cycle of these signals is measured as described above and used to adjust the phases of the clock signals.

## Claims

### Claim 1

A method of conditioning clock signals, the method comprising:
generating a plurality of pairs of complementary clock signals, each clock signal having a phase and a duty cycle;
generating first and second voltages having respective magnitudes corresponding to the duty cycles of first and second clock signals in one of the pairs of complementary clock signals;
comparing the magnitude of the first voltage to the magnitude of the second voltage;
if the magnitude of the first voltage is greater than the magnitude of the second voltage, decreasing the duty cycle of the first clock signal and increasing the duty cycle of the second clock signal until the magnitude of the first voltage is no longer greater than the magnitude of the second voltage; and
if the magnitude of the second voltage is greater than the magnitude of the first voltage, increasing the duty cycle of the first clock signal and decreasing the duty cycle of the second clock signal until the magnitude of the second voltage is no longer greater than the magnitude of the first voltage.

### Claim 2 (depends on 1)

The method of claim 1 wherein the act of generating first and second voltages having respective magnitudes corresponding to the duty cycles of first and second clock signals comprise low-pass filtering the first clock signal to generate the first voltage, and low-pass filtering the second clock signal to generate the second voltage.

### Claim 3 (depends on 1)

The method of claim 1, further comprising adjusting the phase of each of the clock signals in the plurality of pairs of complementary clock signals.

### Claim 4 (depends on 3)

The method of claim 3 wherein the act of adjusting the phase of each of the clock signals in the plurality of pairs of complementary clock signals comprises:
comparing to each other a first set of clock signals that are assigned a predetermined phase difference to provide a first phase comparison signal indicative of the results of the comparison;
comparing to each other a second set of clock signals that are assigned the predetermined phase difference to provide a second phase comparison signal indicative of the results of the comparison, at least one of the clock signals in the second set being different from the clock signals in the first set;
comparing the first phase comparison signal to the second phase comparison signal;
if the comparison of the first phase comparison signal to the second phase comparison signal has a first value, changing the phase of one of the clock signals in one of the first and second sets in a manner that changes the comparison of the clock signals in the first set or the comparison of the clock signals in the second set in a first direction; and
if the comparison of the first phase comparison signal to the second phase comparison signal has a second value, changing the phase of one of the clock signals in one of the first and second sets in a manner that changes the comparison of the clock signals in the first set or the comparison of the clock signals in the second set in a second direction that is different from the first direction.

### Claim 5 (depends on 4)

The method of claim 4 wherein the act of comparing the clock signals in the first set to each other and comparing the clock signals in the second set to each other comprise processing the clock signals in the first set with a first logic function, and processing the clock signals in the second set with a second logic function.

### Claim 6 (depends on 5)

The method of claim 5 wherein the first logic function is the same as the second logic function.

### Claim 7 (depends on 4)

The method of claim 4 wherein the act of comparing the clock signals in the first set to each other comprises generating as the first phase comparison signal a signal having a duty cycle corresponding to the phase relationship between the clock signals in the first set, and wherein the act of comparing the clock signals in the second set to each other comprises generating as the second phase comparison signal a signal having a duty cycle corresponding to the phase relationship between the clock signals in the second set.

### Claim 8 (depends on 7)

The method of claim 7 wherein the act of comparing the first phase comparison signal to the second phase comparison signal comprises comparing the duty cycle of the first phase comparison signal to the duty cycle of the second phase comparison signal.

### Claim 9 (depends on 8)

The method of claim 8 wherein the act of comparing the duty cycle of the first phase comparison signal to the duty cycle of the second phase comparison signal comprises:
generating respective first and second phase comparison voltages having respective magnitudes corresponding to the duty cycles of first and second phase comparison signals; and
comparing the magnitude of the first phage comparison voltage to the magnitude of the second phase comparison voltage.

### Claim 10 (depends on 9)

The method of claim 9 wherein the act of generating respective first and second phase comparison voltages having respective magnitudes corresponding to the duty cycles of first and second phase comparison signals comprises low-pass filtering the first and second phase comparison signals.

### Claim 11 (depends on 4)

The method of claim 4 wherein the act of comparing the first phase comparison signal to the second phase comparison signal comprises:
low-pass filtering the first phase comparison signal to provide a first comparison signal;
low-pass filtering the second phase comparison signal to provide a second comparison signal; and
comparing the magnitude of the first comparison signal to the magnitude of the second comparison signal.

### Claim 12 (depends on 4)

The method of claim 4 wherein the predetermined phase difference comprises 45 degrees.

### Claim 13 (depends on 1, 3)

The method of claim 3, further comprising, after adjusting the phase of each of the clock signals in the plurality of pairs of complementary clock signals, adjusting the duty cycles of each of the clock signals in the plurality of pairs of complementary clock signals by repeating the conditioning the clock signals according to the method of claim 1.

### Claim 14

A method of adjusting the relative phases of each of a plurality clock signals, comprising:
comparing to each other a first set of clock signals that are assigned a predetermined phase difference to provide a first phase comparison signal indicative of the results of the comparison;
comparing to each other a second set of clock signals that are assigned the predetermined phase difference to provide a second phase comparison signal indicative of the results of the comparison, at least one of the clock signals in the second set being different from the clock signals in the first set;
comparing the first phase comparison signal to the second phase comparison signal;
if the comparison of the first phase comparison signal to the second phase comparison signal has a first value, changing the phase of one of the clock signals in one of the first and second sets in a manner that changes the comparison of the clock signals in the first set or the comparison of the clock signals in the second set in a first direction; and
if the comparison of the first phase comparison signal to the second phase comparison signal has a second value, changing the phase of one of the clock signals in one of the first and second sets in a manner that changes the comparison of the clock signals in the first set or the comparison of the clock signals in the second set in a second direction that is different from the first direction.

### Claim 15 (depends on 14)

The method of claim 14 wherein the act of comparing the clock signals in the first set to each other and comparing the clock signals in the second set to each other comprise processing the clock signals in the first set with a first logic function, and processing the clock signals in the second set with a second logic function.

### Claim 16 (depends on 15)

The method of claim 15 wherein the first logic function is the same as the second logic function.

### Claim 17 (depends on 14)

The method of claim 14 wherein the act of comparing the clock signals in the first set to each other comprises generating as the first phase comparison signal a signal having a duty cycle corresponding to the phase relationship between the clock signals in the first set, and wherein the act of comparing the clock signals in the second set to each other comprises generating as the second phase comparison signal a signal having a duty cycle corresponding to the phase relationship between the clock signals in the second set.

### Claim 18 (depends on 17)

The method of claim 17 wherein the act of comparing the first phase comparison signal to the second phase comparison signal comprises comparing the duty cycle of the first phase comparison signal to the duty cycle of the second phase comparison signal.

### Claim 19 (depends on 18)

The method of claim 18 wherein the act of comparing the duty cycle of the first phase comparison signal to the duty cycle of the second phase comparison signal comprises:
generating respective first and second phase comparison voltages having respective magnitudes corresponding to the duty cycles of first and second phase comparison signals; and
comparing the magnitude of the first phage comparison voltage to the magnitude of the second phase comparison voltage.

### Claim 20 (depends on 19)

The method of claim 19 wherein the act of generating respective first and second phase comparison voltages having respective magnitudes corresponding to the duty cycles of first and second phase comparison signals comprises low-pass filtering the first and second phase comparison signals.

### Claim 21 (depends on 14)

The method of claim 14 wherein the act of comparing the first phase comparison signal to the second phase comparison signal comprises:
low-pass filtering the first phase comparison signal to provide a first comparison signal;
low-pass filtering the second phase comparison signal to provide a second comparison signal; and
comparing the magnitude of the first comparison signal to the magnitude of the second comparison signal.

### Claim 22 (depends on 14)

The method of claim 14 wherein the predetermined phase difference comprises 45 degrees.

### Claim 23

A method of conditioning a clock the method comprising:
generating a plurality of pairs of complementary clock signals, each clock signal having a phase and a duty cycle; and
alternating correcting the duty cycle of the clock signals in each of the plurality of pairs of complementary clock signals and setting the phases of the clock signals in each of the plurality of pairs of complementary clock signals until the duty cycle of the clock signals have been corrected and the phases of the clock signals have been set, the duty cycle of the clock signals being corrected and the phases of the clock signals being corrected by:
selecting a first set of the clock signals that are assigned a predetermined phase difference;
selecting a second set of the clock signals that are assigned the predetermined phase difference, at least one of the clock signals in the second set being different from the clock signals in the first set;
generating a first phase comparison signal having a duty cycle corresponding to the phase relationship between the clock signals in the first set;
generating a second phase comparison signal having a duty cycle corresponding to the phase relationship between the clock signals in the second set;
generating first and second duty cycle voltages having respective magnitudes corresponding to the duty cycles of first and second clock signals in each of the pairs of complementary clock signals;
generating first and second phase comparison voltages having respective magnitudes corresponding to the duty cycles of first and second phase comparison signals;
comparing the magnitude of the first duty cycle voltage to the magnitude of the second duty cycle voltage;
if the magnitude of the first duty cycle voltage is greater than the magnitude of the second duty cycle voltage, decreasing the duty cycle of the first clock signal and increasing the duty cycle of the second clock signal until the magnitude of the first duty cycle voltage is no longer greater than the magnitude of the second duty cycle voltage;
if the magnitude of the second duty cycle voltage is greater than the magnitude of the first duty cycle voltage, increasing the duty cycle of the first clock signal and decreasing the duty cycle of the second clock signal until the magnitude of the second duty cycle voltage is no longer greater than the magnitude of the first duty cycle voltage;
comparing the magnitude of the first phase comparison voltage to the magnitude of the second phase comparison voltage;
if the magnitude of the first phase comparison voltage is greater than the magnitude of the second phase comparison voltage, changing the phase of one of the clock signals in one of the first and second sets in a manner that changes the phase relationship between the clock signals in the first set or the second set in a first direction until the magnitude of the first phase comparison voltage is no longer greater than the magnitude of the second phase comparison voltage; and
if the magnitude of the second phase comparison voltage is greater than the magnitude of the first phase comparison voltage, changing the phase of one of the clock signals in one of the first and second sets in a manner that changes the phase relationship between the clock signals in the first set or the second set in a second direction that is opposite the first direction until the magnitude of the second phase comparison voltage is no longer greater than the magnitude of the first phase comparison voltage.

### Claim 24 (depends on 23)

The method of claim 23 wherein the act of generating the first and second duty cycle voltages comprises low-pass filtering the first and second clock signals, respectively, and wherein the act of generating the first and second phase comparison voltages comprise low-pass filtering the first and second phase comparison signals, respectively.

### Claim 25 (depends on 23)

The method of claim 23 wherein the predetermined phase difference comprises 45 degrees.

### Claim 26

A system for conditioning clock signals in a plurality of complementary pairs of the clock signals, each clock signal having a phase and a duty cycle, the system comprising:
a plurality of duty cycle correctors each of which receives the clock signals of a respective one of the pairs of clock signals, the duty cycles of the clock signals output from the duty cycle correctors being controlled by respective duty cycle control signals;
a plurality of delay lines each of which receives the clock signals of a respective one of the pairs of clock signals, the phases of the clock signals output from the delay lines being controlled by respective phase control signals, each of the delay lines being coupled in series with a respective one of the duty cycle correctors;
a first processing circuit having a plurality of input terminals, the first processing circuit being operable to generate at an output terminal a first phase comparison signal having a duty cycle corresponding to a phase relationship between clock signals applied to the input terminals of the first processing circuit;
a second processing circuit having a plurality of input terminals, the second processing circuit being operable to generate at an output terminal a second phase comparison signal having a duty cycle corresponding to a phase relationship between clock signals applied to the input terminals of the second processing circuit;
a comparison circuit having a plurality of input terminals, the comparison circuit being operable to compare the duty cycle of clock signals applied to the input terminals of the comparison circuit and to generate a comparison signal corresponding thereto;
a controller coupled to receive the comparison signal from the comparison circuit, the controller being operable to apply to the duty cycle correctors the respective duty cycle control signals based on the comparison signal and to apply to the delay lines respective phase control signals based on the comparison signal; and
a switching circuit coupled to receive the clock signals from the series combinations of a respective duty cycle correctors and delay lines, and to receive the first and second phase comparison signals from the first and second processing circuits, respectively, the switching circuit being operable in a duty cycle correcting mode to sequentially couple the clock signals of each of the pairs of clock signals to the input terminals of the comparison circuit, the switching circuit being operable in a phase adjustment mode to couple the first and second phase comparison signals of the first and second processing circuits, respectively, to the input terminals of the comparison circuit, the switching circuit further being operable in the phase adjustment mode to sequentially couple to the input terminals of the first processing circuit a first set of clock signals that are assigned a predetermined phase difference while coupling to the input terminals of the second processing circuit a second set of clock signals that are assigned the predetermined phase difference, at least one of the clock signals in the second set being different from the clock signals in the first set.

### Claim 27 (depends on 26)

The clock signal conditioning system of claim 26 wherein the first and second processing circuits comprise respective logic gates.

### Claim 28 (depends on 27)

The clock signal conditioning system of claim 27 wherein the logic gates comprise respective NAND gates.

### Claim 29 (depends on 26)

The clock signal conditioning system of claim 26 wherein the comparison circuit comprises:
a respective low-pass filter coupled to each of the input terminals of the comparison circuit, each of the low-pass filters being structured to output a respective output signal; and
a comparator having a plurality of inputs each of which is coupled to receive an output signal from a respective one of the low-pass filters, the comparator being operable to compare the magnitudes of the output signals from the low-pass filters.

### Claim 30 (depends on 29)

The clock signal conditioning system of claim 29 wherein the comparator is operable to receive output signals from two low-pass filters and to generate a binary signal indicative of the polarity of the comparison between the magnitudes of the output signals from the low-pass filters.

### Claim 31 (depends on 26)

The clock signal conditioning system of claim 26 wherein the switching circuit comprises at least one multiplexer.

### Claim 32 (depends on 31)

The clock signal conditioning system of claim 31 wherein the switching circuit comprises:
a first multiplexer coupled to receive the clock signals of each of the pairs of clock signals and to couple the received the clock signals of a selected pair of the clock signals to respective output terminals;
a second multiplexer coupled to receive the clock signals of each of the pairs and to couple a selected two of the received the clock signals to the input terminals of the first processing circuit;
a third multiplexer coupled to receive the clock signals of each of the pairs and to couple a selected two of the received the clock signals to the input terminals of the second processing circuit; and
a fourth multiplexer having input terminals coupled to the output terminals of the first multiplexer and to the output terminals of the first and second processing circuits, respectively, the fourth multiplexer being operable in the duty cycle correcting mode to couple the output terminals of the first multiplexer to the input terminals of the comparison circuit, and being operable in the phase adjustment mode to couple the output terminals of the first and second processing circuits to the input terminals of the comparison circuit.

### Claim 33

An integrated circuit load board, comprising:
a substrate;
a plurality of integrated circuit sockets mounted on the substrate;
a clock source generating a plurality of complementary pairs of the clock signals, each clock signal having a phase and a duty cycle;
a clock signal conditioning system coupled to receive the clock signals from the clock source, the clock signal conditioning system comprising:
a plurality of duty cycle correctors each of which receives the clock signals of a respective one of the pairs of clock signals, the duty cycles of the clock signals output from the duty cycle correctors being controlled by respective duty cycle control signals;
a plurality of delay lines each of which receives the clock signals of a respective one of the pairs of clock signals, the phases of the clock signals output from the delay lines being controlled by respective phase control signals, each of the delay lines being coupled in series with a respective one of the duty cycle correctors;
a first processing circuit having a plurality of input terminals, the first processing circuit being operable to generate at an output terminal a first phase comparison signal having a duty cycle corresponding to a phase relationship between clock signals applied to the input terminals of the first processing circuit;
a second processing circuit having a plurality of input terminals, the second processing circuit being operable to generate at an output terminal a second phase comparison signal having a duty cycle corresponding to a phase relationship between clock signals applied to the input terminals of the second processing circuit;
a comparison circuit having a plurality of input terminals, the comparison circuit being operable to compare the duty cycle of clock signals applied to the input terminals of the comparison circuit and to generate a comparison signal corresponding thereto;
a controller coupled to receive the comparison signal from the comparison circuit, the controller being operable to apply to the duty cycle correctors the respective duty cycle control signals based on the comparison signal and to apply to the delay lines respective phase control signals based on the comparison signal; and
a switching circuit coupled to receive the clock signals from the series combinations of a respective duty cycle correctors and delay lines, and to receive the first and second phase comparison signals from the first and second processing circuits, respectively, the switching circuit being operable in a duty cycle correcting mode to sequentially couple the clock signals of each of the pairs of clock signals to the input terminals of the comparison circuit, the switching circuit being operable in a phase adjustment mode to couple the first and second phase comparison signals of the first and second processing circuits, respectively, to the input terminals of the comparison circuit, the switching circuit further being operable in the phase adjustment mode to sequentially couple to the input terminals of the first processing circuit a first set of clock signals that are assigned a predetermined phase difference while coupling to the input terminals of the second processing circuit a second set of clock signals that are assigned the predetermined phase difference, at least one of the clock signals in the second set being different from the clock signals in the first set; and
an integrated test circuit mounted on the substrate and coupled to the integrated circuit sockets and to the clock signal conditioning system, the integrated test circuit being operable to apply test signals to the integrated circuit sockets and to receive response signals from the integrated circuit sockets, the integrated test circuit having an output port from which test results data derived from the response signals are output, the integrated test circuit being operable to alter the relative timing at which the test signals are applied to the integrated circuit sockets based on a plurality of clock signals received from the clock signal conditioning system.

### Claim 34 (depends on 33)

The integrated circuit load board of claim 33 wherein the first and second processing circuits comprise respective logic gates.

### Claim 35 (depends on 34)

The integrated circuit load board of claim 34 wherein the logic gates comprise respective NAND gates.

### Claim 36 (depends on 33)

The integrated circuit load board of claim 33 wherein the comparison circuit comprises:
a respective low-pass filter coupled to each of the input terminals of the comparison circuit, each of the low-pass filters being structured to output a respective output signal; and
a comparator having a plurality of inputs each of which is coupled to receive an output signal from a respective one of the low-pass filters, the comparator being operable to compare the magnitudes of the output signals from the low-pass filters.

### Claim 37 (depends on 36)

The integrated circuit load board of claim 36 wherein the comparator is operable to receive output signals from two low-pass filters and to generate a binary signal indicative of the polarity of the comparison between the magnitudes of the output signals from the low-pass filters.

### Claim 38 (depends on 33)

The integrated circuit load board of claim 33 wherein the switching circuit comprises at least one multiplexer.

### Claim 39 (depends on 38)

The integrated circuit load board of claim 38 wherein the switching circuit comprises:
a first multiplexer coupled to receive the clock signals of each of the pairs of clock signals and to couple the received the clock signals of a selected pair of the clock signals to respective output terminals;
a second multiplexer coupled to receive the clock signals of each of the pairs and to couple a selected two of the received the clock signals to the input terminals of the first processing circuit;
a third multiplexer coupled to receive the clock signals of each of the pairs and to couple a selected two of the received the clock signals to the input terminals of the second processing circuit; and
a fourth multiplexer having input terminals coupled to the output terminals of the first multiplexer and to the output terminals of the first and second processing circuits, respectively, the fourth multiplexer being operable in the duty cycle correcting mode to couple the output terminals of the first multiplexer to the input terminals of the comparison circuit, and being operable in the phase adjustment mode to couple the output terminals of the first and second processing circuits to the input terminals of the comparison circuit.