# US 7,612,617 B2 · Voltage-controlled oscillator gain calibration for two-point modulation in a phase-locked loop

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 7,612,617 B2
- Document ID: US7612617B2
- Status: Granted
- Kind: B2
- Application number: 12/040,875
- Filed: 2008-03-01
- Published: 2009-09-03
- Granted: 2009-11-03
- Earliest claimed: 2008-03-01
- Assignees: Skyworks Solutions, Inc.
- Inventors: Rajasekhar Pullela; Morten Damgaard; Shahrzad Tadjpour; John E. Vasa; Hoon Lee
- Web page: https://patentgrep.com/patent/US7612617B2

## CPC

- H03C 3/0925: {applying frequency modulation at the divider in the feedback loop}
- H03C 3/0933: {using fractional frequency division in the feedback loop of the phase locked loop}
- H03C 3/0941: {applying frequency modulation at more than one point in the loop}
- H03C 3/095: {applying frequency modulation to the loop in front of the voltage controlled oscillator}
- H03C 3/0991: {including calibration means or calibration methods}
- H03C: MODULATION (masers or lasers H01S; coding, decoding or code conversion H03M)

## Abstract

A phase-locked loop (PLL) is arranged to receive high-pass data at a first input and low-pass data at a second input. A first digital input is coupled to a primary path through a digital-to-analog converter (DAC) and a second digital input is coupled to a feedback path of the PLL. The controller provides the first input and the second input during a calibration procedure. The controller adjusts first and second control inputs in an attempt to keep the input voltage to a voltage-controlled oscillator (VCO) in the PLL constant while determining the gain of the VCO in Hz/LSB.

## Claims

### Claim 1

A method for measuring gain of a voltage-controlled oscillator (VCO), comprising:
applying a first control signal to a phase-locked loop (PLL);
allowing the PLL to settle;
recording a first voltage at the input to the VCO in the PLL;
applying a second control signal different from the first control signal to the PLL;
adjusting the feedback path to compensate for an expected change in the voltage at the input to the VCO;
recording a second voltage at the input to the VCO;
determining if time is available to compare the measured change in voltage with a threshold value, wherein when time is unavailable proceeding to calculate the gain of the VCO and terminating the method, otherwise when time is available;
determining whether a difference between the second voltage and the first voltage at the input to the VCO is within a specified tolerance;
when the difference between the second voltage and the first voltage is not within a specified tolerance, further adjusting the feedback path in response to the difference;
repeating the recording, determining and further adjusting steps until the difference between the second voltage and the first voltage at the input to the VCO is within the specified tolerance; and
calculating the gain of the VCO.

### Claim 2 (depends on 1)

The method of claim 1, wherein applying the first control signal comprises communicating a first digital word to a digital-to-analog converter.

### Claim 3 (depends on 1)

The method of claim 1, wherein recording one of a first voltage and a second voltage at the input to the VCO comprises an analog-to-digital conversion.

### Claim 4 (depends on 1)

The method of claim 1, wherein applying the second control signal is responsive to an estimate of the gain of the VCO.

### Claim 5 (depends on 4)

The method of claim 4, wherein applying the second control signal comprises communicating a second digital word to a digital-to-analog converter.

### Claim 6 (depends on 1)

The method of claim 1, wherein adjusting the feedback path comprises programming a fractional divider.

### Claim 7 (depends on 6)

The method of claim 6, wherein programming the fractional divider compensates for the change in frequency due to a digital-to-analog conversion.

### Claim 8 (depends on 1)

The method of claim 1, wherein applying the first control signal to the PLL further comprises using a PLL having a bandwidth of approximately 100 kHz.

### Claim 9 (depends on 1)

The method of claim 1, wherein calculating the gain of the VCO comprises determining a ratio of frequency/bit.

### Claim 10 (depends on 9)

The method of claim 9, wherein calculating the gain of the VCO comprises determining frequency using a difference of an initial divider setting to a final divider setting multiplied by a reference frequency.

### Claim 11 (depends on 1)

The method of claim 1, wherein recording the first and second voltages comprises using an analog-to-digital converter (ADC).

### Claim 12 (depends on 11)

The method of claim 11, wherein an ADC gain/step is known within ten percent accuracy.

### Claim 13 (depends on 12)

The method of claim 12, wherein an estimated value of the gain of the VCO is known within ten percent accuracy.

### Claim 14 (depends on 13)

The method of claim 13, wherein the gain of the VCO is calculated within one percent accuracy with one pass through the method.

### Claim 15

A system, comprising:
a phase-locked loop (PLL) arranged to receive high-pass data at a first input and low-pass data at a second input, the first input coupled to a primary path and the second input coupled to a feedback path;
a controller coupled to the first input and the second input, the controller configured to adjust first and second control inputs in an attempt to keep the input voltage to a voltage-controlled oscillator in the PLL constant to determine a gain of the VCO.

### Claim 16 (depends on 15)

The system of claim 15, wherein the first control input is applied to a digital-to analog converter (DAC), the output of the DAC being applied to an input of the VCO.

### Claim 17 (depends on 15)

The system of claim 15, wherein respective digital inputs applied to a fractional divider in the feedback path and to a digital-to-analog converter are shaped to result in reduced settling times for the PLL.

### Claim 18 (depends on 15)

The system of claim 15, wherein the second control input is applied to a fractional divider.

### Claim 19 (depends on 15)

The system of claim 15, wherein the controller is actuated prior to a transmission burst in a transceiver that applies two-point modulation.

### Claim 20 (depends on 18)

The system of claim 18, wherein the controller and PLL are implemented within a GSM/EDGE single integrated-circuit transceiver.