# US 7,612,614 B2 · Device and method for biasing a transistor amplifier > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,612,614 B2 - Document ID: US7612614B2 - Status: Granted - Kind: B2 - Application number: 12/416,538 - Filed: 2009-04-01 - Published: 2009-07-23 - Granted: 2009-11-03 - Earliest claimed: 2007-07-09 - Assignees: Kontel Data System Limited - Inventors: Ping Wai Li; Cong Ke Li; Wei Wang - Web page: https://patentgrep.com/patent/US7612614B2 ## CPC - H03F 1/30: Modifications of amplifiers to reduce influence of variations of temperature or supply voltage {or other physical parameters (in differential amplifiers H03F3/45479)} - H03F 3/45475: {using IC blocks as the active amplifying circuit} - H03H 7/0107: {Non-linear filters} - H03H 7/0153: {Electrical filters; Controlling thereof} - H03H 11/1291: {Current or voltage controlled filters} - H03F 2200/213: A variable capacitor being added in the input circuit, e.g. base, gate, of an amplifier stage - H03F 2203/45136: One differential amplifier in IC-block form being shown - H03F 2203/45244: the differential amplifier contains one or more explicit bias circuits, e.g. to bias the tail current sources, to bias the load transistors - H03F 2203/45622: the IC comprising a voltage generating circuit - H03F: AMPLIFIERS - H03H: IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS (waveguides, resonators, lines or other devices of the waveguide type H01P) ## Abstract Provided is circuitry for biasing a transistor amplifier with a DC-voltage signal, the transistor amplifier having a first input terminal, a second input terminal, and an output terminal coupled to the second input terminal. The circuitry includes a sensor capacitor connected to the first input terminal and an impedance transistor arranged in parallel with said capacitor, the transistor and capacitor forming a low-pass filter. The circuitry also includes a biasing circuit configured to controllably vary a DC-voltage signal for operatively biasing the amplifier, the biasing circuit including a cascaded current arrangement configured to subdivide a reference current into smaller currents for selectively generating voltage potentials for biasing the impedance transistor to adjustably filter a noise component of the DC-voltage signal via the low-pass filter before the DC-voltage signal is provided to the first input terminal. ## Claims ### Claim 1 A circuit arrangement for biasing a transistor amplifier with a DC-voltage signal, the transistor amplifier having a first input terminal, a second input terminal, and an output terminal coupled to the second input terminal, wherein said circuitry comprises: a sensor capacitor connected to the first input terminal; an impedance transistor arranged in parallel with said capacitor, the transistor and capacitor forming a low-pass filter; and a biasing circuit configured to controllably vary the DC-voltage signal for operatively biasing the amplifier, the biasing circuit including a cascaded current arrangement configured to subdivide a reference current into smaller currents for selectively generating voltage potentials for biasing the impedance transistor to adjustably filter a noise component of the DC-voltage signal via the low-pass filter before the DC-voltage signal is provided to the first input terminal. ### Claim 2 (depends on 1) A circuit arrangement of claim 1, wherein the cascaded current arrangement includes a number of transistor cells to facilitate subdivision of a reference current IREF by m number of stages to IREF/NM−1. ### Claim 3 (depends on 2) A circuit arrangement of claim 2, wherein each transistor cell includes two transistors M1 and M2 arranged in parallel with a transistor Ms1 having a W/L ratio of N/N−1, where N is the ratio of current in the cell, inserted between M1 and M2 and connected to a source terminal of transistor M2. ### Claim 4 (depends on 3) A circuit arrangement of claim 3, wherein the transistor cell includes PMOS transistors. ### Claim 5 (depends on 4) A circuit arrangement of claim 4, wherein the cascaded current arrangement includes a biasing voltage Vbias attached to a source terminal of the first PMOS transistor of the first transistor cell with drain terminals of all the transistors of each cell connected to ground. ### Claim 6 (depends on 5) A circuit arrangement of claim 5, wherein n-wells of the PMOS transistors of the transistor cells are connected to their respective source terminals. ### Claim 7 (depends on 6) A circuit arrangement of claim 6, wherein, the cascaded arrangement includes a number of unity gain amplifiers for driving the n-wells of successive transistor cells in the cascaded arrangement. ### Claim 8 (depends on 7) A circuit arrangement of claim 7, wherein the impedance transistor is driven via an amplifier arranged in a negative feedback loop with a positive input terminal thereof connected to Vbias and a negative terminal thereof connected to an output of a unity gain amplifier of a last transistor cell. ### Claim 9 A method for biasing a transistor amplifier with a DC-voltage signal, said amplifier having a first input terminal, a second input terminal, and an output terminal coupled to the second input terminal, the method comprising: operatively coupling a sensor capacitor and parallel impedance transistor to the first input terminal, the transistor and capacitor forming a low-pass filter, and a biasing circuit to the impedance transistor, the biasing circuit including a cascaded current arrangement configured to subdivide a reference current into smaller currents for selectively generating voltage potentials for biasing the impedance transistor to adjustably filter a noise component of the DC-voltage signal via the low-pass filter before the DC-voltage signal is provided to the first input terminal; and selectively adjusting the DC-voltage signal with the biasing circuit to filter the noise component. ### Claim 10 A device for biasing a transistor amplifier with a DC-voltage signal, the transistor amplifier having a first input terminal, a second input terminal, and an output terminal coupled to the second input terminal, wherein said device comprises: an impedance transistor forming part of a low-pass filter; and a biasing circuit configured to controllably vary the DC-voltage signal for operatively biasing the amplifier, the biasing circuit including a cascaded current arrangement configured to subdivide a reference current into smaller currents for selectively generating voltage potentials for biasing the impedance transistor to adjustably filter a noise component of the DC-voltage signal via the low-pass filter before the DC-voltage signal is provided to the first input terminal. ### Claim 11 A low-pass filter adapted for use in filtering out a voltage ripple in a supply voltage signal, the voltage ripple being generated by a voltage multiplier device during voltage step-up conversion of the supply voltage signal before said supply voltage signal is fed to a capacitive sensor, the low-pass filter including a capacitor operatively coupled with a first and second diode, said first and second diodes being adapted for operative coupling in parallel between a terminal of the capacitor and an output terminal of the voltage multiplier device, said diodes being arranged in reverse polarity relative to each other in parallel. ### Claim 12 (depends on 11) A low-pass filter as claimed in claim 11, wherein said low-pass filter is fabricated on an integrated circuit chip. ### Claim 13 (depends on 11) A low-pass filter as claimed in claim 11, wherein the capacitive sensor and the voltage multiplier device are fabricated on the integrated circuit chip.