# US 7,612,605 B2 · Bootstrap voltage generating circuits

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- Number: US 7,612,605 B2
- Document ID: US7612605B2
- Status: Granted
- Kind: B2
- Application number: 11/705,642
- Filed: 2007-02-12
- Published: 2008-08-14
- Granted: 2009-11-03
- Earliest claimed: 2007-02-12
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Shao-Yu Chou; Yen-Huei Chen; Jui-Jen Wu; Gary Chan
- Web page: https://patentgrep.com/patent/US7612605B2

## CPC

- H02M 3/07: using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps}
- G11C 5/147: {Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence)}
- H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A bootstrap voltage generating circuit includes a bias circuit having a first end coupled to a first power source node having an operation voltage, and a second end coupled to a low voltage reference potential, wherein a voltage at the first end is related to the operation voltage in a non-linear way; a charging capacitor having a first end coupled to the load circuit; a charging path between a second end of the charging capacitor and the first end of the bias circuit, wherein the charging path is responsive to a clock signal; a discharging path between the second end of the charging capacitor and the low voltage reference potential, wherein the discharging path is responsive to the clock signal; and a switch circuit connected to the first end of the charging capacitor for setting a voltage thereon, wherein the switch circuit is responsive to the clock signal.

## Claims

### Claim 1

A bootstrap voltage generating circuit for generating a bootstrap voltage on a load circuit having a load capacitance, wherein the bootstrap voltage generating circuit comprises:
a bias circuit having a first end coupled to a first power source node having an operation voltage, and a second end coupled to a low voltage reference potential, wherein a voltage at the first end is related to the operation voltage in a non-linear way, and wherein the bias circuit comprises a diode;
a charging capacitor having a first end coupled to the load circuit;
a charging path between a second end of the charging capacitor and the first end of the bias circuit, wherein the charging path is responsive to a clock signal;
a discharging path between the second end of the charging capacitor and the low voltage reference potential, wherein the discharging path is responsive to the clock signal; and
a switch circuit connected to the first end of the charging capacitor for setting a voltage at the first end of the charging capacitor, wherein the switch circuit is responsive to the clock signal, and wherein the switch circuit is configured to control the bootstrap voltage generating circuit to output both a positive voltage and a negative voltage at the first end of the charging capacitor.

### Claim 2 (depends on 1)

The bootstrap voltage generating circuit of claim 1, wherein the charging path comprises a PMOS transistor having a source connected to the first end of the bias circuit, the discharging path comprises an NMOS device having a source connected to the low voltage reference potential, wherein a drain of the PMOS transistor is connected to a drain of the NMOS transistor, and wherein a gate of the PMOS transistor and a gate of the NMOS transistor are connected to the clock signal.

### Claim 3 (depends on 1)

The bootstrap voltage generating circuit of claim 1, wherein the first end of the bias circuit is at a constant voltage lower than the operation voltage, and wherein the constant voltage is independent from a variation in the operation voltage.

### Claim 4 (depends on 1)

The bootstrap voltage generating circuit of claim 1, wherein the bias circuit comprises a resistive device, and wherein the voltage at the first end of the bias circuit is proportional to a resistance of the resistive device.

### Claim 5 (depends on 4)

The bootstrap voltage generating circuit of claim 4, wherein the bias circuit further comprises an NMOS transistor serially coupled to the resistive device, wherein a gate and a drain of the NMOS device are interconnected.

### Claim 6 (depends on 1)

The bootstrap voltage generating circuit of claim 1 further comprising a current source coupled between the operation voltage and the first end of the bias circuit.

### Claim 7 (depends on 1)

The bootstrap voltage generating circuit of claim 1, wherein the low voltage reference potential is ground.

### Claim 8

A bootstrap voltage generating circuit for generating a bootstrap voltage on a load circuit having a load capacitance, wherein the bootstrap voltage generating circuit comprises:
a current source for providing a current;
a bias circuit receiving the current, wherein the bias circuit has a first end, and a second end connected to a reference potential, and wherein a voltage at the first end of the bias voltage is a function of a resistance of a resistive device, and wherein the bias circuit comprises a diode;
a PMOS transistor having a source coupled to the first end of the bias circuit;
an NMOS transistor having a drain connected to a drain of the PMOS transistor, and a gate connected to a gate of the PMOS transistor, wherein the gates of the PMOS transistor and the NMOS transistor are coupled to a clock signal;
a charging capacitor having a first end coupled to the drains of the PMOS transistor and the NMOS transistor, and a second end coupled to the load circuit; and
a switch circuit connected to a second end of the charging capacitor for setting a voltage at the second end of the charging capacitor, wherein the switch circuit is responsive to the clock signal, and wherein the switch circuit is configured to control the bootstrap voltage generating circuit to output a positive voltage and a negative voltage at the second end of the charging capacitor.

### Claim 9 (depends on 8)

The bootstrap voltage generating circuit of claim 8, wherein the voltage at the first end of the bias voltage is not a function of a power supply voltage of the bootstrap voltage generating circuit.

### Claim 10 (depends on 8)

The bootstrap voltage generating circuit of claim 8, wherein the bias circuit further comprises an additional NMOS transistor coupled in series with the resistive device, and wherein a gate and a drain of the additional NMOS transistor are interconnected, and wherein a voltage at the first end of the bias circuit is linear to a threshold voltage of the additional NMOS transistor.

### Claim 11 (depends on 8)

The bootstrap voltage generating circuit of claim 8, wherein the bias circuit further comprises a diode coupled in series with the resistive device.

### Claim 12 (depends on 8)

The bootstrap voltage generating circuit of claim 8 further comprising:
an additional current source for providing an additional current;
an additional bias circuit receiving the additional current, wherein the additional bias circuit has a first end, and a second end connected to the reference potential, and wherein a voltage at the first end of the additional bias circuit is independent from a drift of the power supply voltage of the bootstrap voltage generating circuit;
an additional PMOS transistor having a source coupled to the first end of the additional bias circuit;
an additional NMOS transistor having a drain connected to a drain of the additional PMOS transistor, and a gate connected to a gate of the additional PMOS transistor, wherein the gates of the additional PMOS and the additional NMOS transistor are coupled to the clock signal;
an additional charging capacitor having a first end coupled to the drains of the additional PMOS transistor and the additional NMOS transistor; and
an additional switch circuit connected to a second end of the additional charging capacitor for setting an additional voltage at the second end of the additional charging capacitor, wherein the additional switch circuit is responsive to an inversed phase of the clock signal, and wherein the voltage set by the switch circuit is the power supply voltage, and the additional voltage set by the additional switch circuit is the reference potential.

### Claim 13 (depends on 8)

The bootstrap voltage generating circuit of claim 8, wherein the current source is coupled between the first end of the bias circuit and an operation voltage of the bootstrap voltage generating circuit, and wherein a drain of the NMOS transistor is connected to the reference potential.