# US 7,612,594 B2 · Latch circuit and semiconductor integrated circuit having the same

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- Number: US 7,612,594 B2
- Document ID: US7612594B2
- Status: Granted
- Kind: B2
- Application number: 11/889,821
- Filed: 2007-08-16
- Published: 2008-02-28
- Granted: 2009-11-03
- Earliest claimed: 2006-08-25
- Assignees: Panasonic Corporation
- Inventors: Kouhei Fukuoka
- Web page: https://patentgrep.com/patent/US7612594B2

## CPC

- H03K 3/356113: {using additional transistors in the input circuit}
- H03K 3/013: Modifications of generator to prevent operation by noise or interference
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A latch circuit includes first, second, and third inverter circuits, a switching element, and a capacitor element. The first inverter circuit and the second inverter circuit are cross-connected to each other. The third inverter circuit logically inverts an output from the first inverter circuit. The switching element is connected between the output terminal of the second inverter circuit and the output terminal of the third inverter circuit. The capacitor element is connected between the output terminal of the third inverter circuit and a reference voltage node.

## Claims

### Claim 1

A latch circuit comprising:
first and second inverter circuits cross-connected to each other;
a third inverter circuit for receiving an output from the first inverter circuit to output a logically inverted value of the output;
a switching element connected between an output terminal of the second inverter circuit and an output terminal of the third inverter circuit; and
a capacitor element connected between the output terminal of the third inverter circuit and a constant reference voltage node.

### Claim 2 (depends on 1)

The latch circuit according to claim 1, comprising:
a fourth inverter circuit for receiving an output from the second inverter circuit to output a logically inverted value of the output;
a switching element connected between the output terminal of the first inverter circuit and an output terminal of the fourth inverter circuit; and
a capacitor element connected between the output terminal of the fourth inverter circuit and the constant reference voltage node.

### Claim 3 (depends on 1)

The latch circuit according to claim 1, wherein the third inverter circuit is a tristate inverter circuit.

### Claim 4 (depends on 1)

The latch circuit according to claim 1, wherein the switching element is a MOS transistor switch.

### Claim 5 (depends on 1)

The latch circuit according to claim 1, wherein the switching element is a transfer gate.

### Claim 6 (depends on 1)

The latch circuit according to claim 1, wherein the capacitor element is a trench capacitor element.

### Claim 7 (depends on 1)

The latch circuit according to claim 1, wherein the capacitor element is a MOS capacitor.

### Claim 8 (depends on 1)

A semiconductor integrated circuit including the latch circuit according to claim 1, wherein the capacitor element is arranged to fill an empty space in the semiconductor integrated circuit.

### Claim 9 (depends on 1)

A semiconductor integrated circuit comprising:
the latch circuit according to claim 1;
a clock gate circuit for controlling the presence/absence of outputting of an input clock signal on the basis of a control signal; and
an input control circuit for controlling the presence/absence of inputting of a data signal to the latch circuit in synchronism with an output signal from the clock gate circuit,
wherein the switching element operates in response to the control signal.

### Claim 10 (depends on 1)

A semiconductor integrated circuit comprising:
the latch circuit according to claim 1; and
a switching control circuit for controlling a switching operation of the switching element in synchronism with switching of operation frequencies of the latch circuit.

### Claim 11 (depends on 1)

A semiconductor integrated device comprising:
the latch circuit according to claim 1; and
a switching control circuit for controlling a switching operation of the switching element in synchronism with switching of operation voltages of the latch circuit.

### Claim 12 (depends on 1)

A semiconductor integrated circuit comprising:
the latch circuit according to claim 1; and
a switching control circuit for detecting switching of operation voltages applied to the latch circuit to control the switching element to an ON state during a switching period.

### Claim 13 (depends on 1)

A static semiconductor memory comprising the latch circuit according to claim 1.

### Claim 14 (depends on 1)

A master-slave-type flip-flop circuit comprising the latch circuit according to claim 1 as at least one of a master latch circuit and a slave latch circuit.

### Claim 15 (depends on 1)

An information appliance comprising the latch circuit according to claim 1.

### Claim 16 (depends on 1)

A communication appliance comprising the latch circuit according to claim 1.

### Claim 17 (depends on 1)

An AV appliance comprising the latch circuit according to claim 1.

### Claim 18 (depends on 1)

A mobile appliance comprising the latch circuit according to claim 1.