# US 7,612,591 B2 · DLL circuit of semiconductor memory apparatus and method of delaying and locking clock in semiconductor memory apparatus > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,612,591 B2 - Document ID: US7612591B2 - Status: Granted - Kind: B2 - Application number: 12/185,835 - Filed: 2008-08-05 - Published: 2008-11-27 - Granted: 2009-11-03 - Earliest claimed: 2006-03-07 - Assignees: Hynix Semiconductor Inc. - Inventors: Kyoung Nam Kim - Web page: https://patentgrep.com/patent/US7612591B2 ## CPC - H03L 7/0814: {the phase shifting device being digitally controlled} - G11C 7/1072: {for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories} - G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management - G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device} - G11C 11/4076: Timing circuits (for regeneration management G11C11/406) - H03L 7/0816: {the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input} - H03L 7/091: the phase or frequency detector using a sampling device (H03L7/087 takes precedence) - H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A DLL circuit of a semiconductor memory apparatus includes a frequency sensing unit that generates and outputs a high frequency signal and a low frequency signal on the basis of a CAS latency signal. A clock dividing unit divides the frequency of an internal clock by a predetermined value and generates a divided clock in response with whether the high frequency signal is enabled or the low frequency signal is enabled. A phase sensing unit that switches a reference clock and a comparison clock, compares the phases thereof in accordance with whether the high frequency signal is enabled or the low frequency signal is enabled, selectively switches first and second phase control signals generated on the basis of the comparison result, and outputs the switched signals. ## Claims ### Claim 1 A DLL circuit of a semiconductor memory apparatus comprising: a clock dividing unit configured to receive a high frequency signal, a low frequency signal, and an internal clock thereby generating a divided clock, to output the internal clock as the divided clock when the low frequency signal is enabled, and to divide the internal clock when the high frequency clock is enabled. ### Claim 2 (depends on 1) The DLL circuit of a semiconductor memory apparatus of claim 1, wherein the clock dividing unit includes: a first divided clock generator configured to receive the internal clock and output the divided clock when the low frequency signal is enabled; and a second divided clock generator configured to receive the internal clock and divide the internal clock when the high frequency signal is enabled. ### Claim 3 (depends on 1) The DLL circuit of a semiconductor memory apparatus of claim 1, further comprising: a frequency sensing unit configured to generate the high frequency signal and the low frequency signal. ### Claim 4 (depends on 3) The DLL circuit of a semiconductor memory apparatus of claim 3, wherein the frequency sensing unit includes: a low frequency signal generator configured to generate the low frequency signal when a control signal shorter than a predetermined length is enabled; and a high frequency signal generator configured to generate the high frequency signal when the control signal longer than the predetermined length is enabled. ### Claim 5 (depends on 4) The DLL circuit of a semiconductor memory apparatus of claim 4, wherein the control signal of the frequency sensing unit is a CAS latency signal. ### Claim 6 (depends on 4) The DLL circuit of a semiconductor memory apparatus of claim 4, wherein the control signal of the frequency sensing unit is an external signal. ### Claim 7 A DLL circuit of a semiconductor memory apparatus comprising: a phase sensing unit configured to receive a high frequency signal, a low frequency signal, an internal clock and a feedback clock thereby outputting a first phase control signal and a second phase control signal, wherein the phase sensing unit is configured to compare the internal clock as a reference clock with the feedback clock as a comparing clock, thereby generating the first and second phase control signals when the high frequency signal is enabled; and to compare the feedback clock as the reference clock with the internal clock as the comparing clock thereby generating the first and second phase control signals having phases that are opposite to the phases of the first and second phase control signal when the high frequency signal is enabled. ### Claim 8 (depends on 7) The DLL circuit of a semiconductor memory apparatus of claim 7, wherein the phase sensing unit includes: a reference clock generator configured to receive a first clock and the feedback clock as input and to generate the reference clock having a phase on the basis of the first clock or the feedback clock in response to whether the low frequency signal is enabled or the high frequency signal is enabled; a comparison clock generator configured to receive the first clock and the feedback clock as input and to generate the comparison clock on the basis of the first clock or the feedback clock in response to whether the low frequency signal is enabled or the high frequency signal is enabled; a phase sensor configured to receive the reference clock and the comparison clock as input and to sense a phase difference between the reference clock and the comparison clock and to generate and output first and second delay signals; a first phase control signal generator configured to receive the first and second delay signals as input and to generate the first phase control signal on the basis of the first and second delay signals in response to whether the low frequency signal is enabled or the high frequency signal is enabled; and a second phase control signal generator configured to receive the first and second delay signals as input and to generate the second phase control signal on the basis of the first and second delay signals in response to whether the low frequency signal is enabled or the high frequency signal is enabled. ### Claim 9 (depends on 7) The DLL circuit of a semiconductor memory apparatus of claim 7, further comprising: a frequency sensing unit configured to generate the high frequency signal and the low frequency signal. ### Claim 10 (depends on 9) The DLL circuit of a semiconductor memory apparatus of claim 9, wherein the frequency sensing unit includes: a low frequency signal generator configured to generate the low frequency signal when a control signal shorter than a predetermined length is enabled; and a high frequency signal generator configured to generate the high frequency signal when the control signal longer than the predetermined length is enabled. ### Claim 11 (depends on 10) The DLL circuit of a semiconductor memory apparatus of claim 10, wherein the control signal of the frequency sensing unit is a CAS latency signal. ### Claim 12 (depends on 10) The DLL circuit of a semiconductor memory apparatus of claim 10, wherein the control signal of the frequency sensing unit is an external signal. ### Claim 13 A DLL circuit of a semiconductor memory apparatus comprising: a frequency sensing unit configured to generate and output a high frequency signal or a low frequency signal on the basis of a control signal; a clock dividing unit configured to receive the high frequency signal, the low frequency signal and an internal clock thereby generating a divided clock, to output the internal clock as the divided clock when the low frequency signal is enabled, and to divide the internal clock when the high frequency clock is enabled; and a phase sensing unit configured to receive a high frequency signal, a low frequency signal, an internal clock and a feedback clock thereby outputting a first phase control signal and a second phase control signal, wherein the phase sensing unit is configured to compare the internal clock as a reference clock with the feedback clock as a comparing clock, thereby generating the first and second phase control signals when the high frequency signal is enabled; and to compare the feedback clock as the reference clock with the internal clock as the comparing clock thereby generating the first and second phase control signals having phases that are opposite to the phases of the first and second phase control signal when the high frequency signal is enabled. ### Claim 14 (depends on 13) The DLL circuit of a semiconductor memory apparatus of claim 13, wherein the clock dividing unit includes: a first divided clock generator configured to receive the internal clock and output the divided clock when the low frequency signal is enabled; and a second divided clock generator configured to receive the internal clock and divide the internal clock when the high frequency signal is enabled. ### Claim 15 (depends on 13) The DLL circuit of a semiconductor memory apparatus of claim 13, wherein the frequency sensing unit includes: a low frequency signal generator configured to generate the low frequency signal when a control signal shorter than a predetermined length is enabled; and a high frequency signal generator configured to generate the high frequency signal when the control signal longer than the predetermined length is enabled. ### Claim 16 (depends on 13) The DLL circuit of a semiconductor memory apparatus of claim 13, wherein the phase sensing unit includes: a reference clock generator configured to receive a first clock and the feedback clock as input and to generate the reference clock having a phase on the basis of the first clock or the feedback clock in response to whether the low frequency signal is enabled or the high frequency signal is enabled; a comparison clock generator configured to receive the first clock and the feedback clock as input and to generate the comparison clock on the basis of the first clock or the feedback clock in response to whether the low frequency signal is enabled or the high frequency signal is enabled; a phase sensor configured to receive the reference clock and the comparison clock as input and to sense a phase difference between the reference clock and the comparison clock and to generate and output first and second delay signals; a first phase control signal generator configured to receive the first and second delay signals as input and to generate a first phase control signal on the basis of the first and second delay signals in response to whether the low frequency signal is enabled or the high frequency signal is enabled; and a second phase control signal generator configured to receive the first and second delay signals as input and to generate a second phase control signal on the basis of the first and second delay signals in response to whether the low frequency signal is enabled or the high frequency signal is enabled.