# US 7,612,587 B2 · Semiconductor circuits > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,612,587 B2 - Document ID: US7612587B2 - Status: Granted - Kind: B2 - Application number: 11/835,406 - Filed: 2007-08-07 - Published: 2008-09-11 - Granted: 2009-11-03 - Earliest claimed: 2007-03-06 - Assignees: Nanya Technology Corporation - Inventors: Wen-Chang Cheng - Web page: https://patentgrep.com/patent/US7612587B2 ## CPC - H03K 19/017581: {programmable} - G11C 5/14: Power supply arrangements {, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels} - G11C 5/143: {Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels (G11C5/148 takes precedence); Switching between alternative supplies (G11C5/141 takes precedence)} - G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management - G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device} - G11C 11/4074: Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits - G11C 11/4076: Timing circuits (for regeneration management G11C11/406) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Semiconductor circuit capable of selecting a corresponding adjusting parameter to adjust the received signal according to different voltages and frequencies. A voltage detector detects a voltage level of an external power voltage to generate a voltage detection signal, a frequency detector detects frequency of a main clock to generate a frequency detection signal, and a signal adjustment unit receives a first signal and selects one of a plurality of different adjusting parameters to adjust the first signal according to the voltage detection signal and the frequency detection signal. ## Claims ### Claim 1 A semiconductor circuit, comprising: a voltage detector detecting a voltage level of an external power voltage to generate a voltage detection signal; a frequency detector detecting frequency of a main clock to generate a frequency detection signal; and a signal adjustment unit receiving a first signal, and selecting one of a plurality of different adjusting parameters to adjust the first signal to generate a plurality of second signals and selectively output one of the second signals according to the voltage detection signal and the frequency detection signal. ### Claim 2 (depends on 1) The semiconductor circuit as claimed in claim 1, wherein the signal adjustment unit comprises a plurality of adjustment units with different adjusting parameters. ### Claim 3 (depends on 2) The semiconductor circuit as claimed in claim 2, wherein the signal adjustment unit selects one of the adjustment units to adjust the first signal according to the voltage detection signal and the frequency detection signal. ### Claim 4 (depends on 1) The semiconductor circuit as claimed in claim 1, wherein the adjusting parameters are delay times. ### Claim 5 (depends on 1) The semiconductor circuit as claimed in claim 1, wherein the adjusting parameters are amplification ratios. ### Claim 6 (depends on 1) The semiconductor circuit as claimed in claim 1, wherein the voltage detector comprises: a voltage dividing unit coupled between the external power voltage and a ground voltage to generate a divided voltage; and a comparator comparing the divided voltage and an internal reference voltage to generate the voltage detection signal with different logic levels. ### Claim 7 (depends on 1) The semiconductor circuit as claimed in claim 1, wherein the semiconductor device is disposed in a core logic unit of a chip. ### Claim 8 A semiconductor memory module, comprising: a clock generator generating a main clock; and a core logic unit powered by an external power voltage and comprising: a voltage detector detecting a voltage level of the external power voltage to generate a voltage detection signal; a frequency detector detecting frequency of the main clock to generate a frequency detection signal; and a signal adjustment unit receiving a first signal, and obtaining a present operating region of the core logic unit and selecting one of a plurality of different parameters to adjust the first signal to generate a plurality of second signals and selectively output one of the second signals according to the voltage detection signal and the frequency detection signal. ### Claim 9 (depends on 8) The semiconductor memory module as claimed in claim 8, wherein the signal adjustment unit comprises a plurality of adjustment units with the different adjusting parameters. ### Claim 10 (depends on 9) The semiconductor memory module as claimed in claim 9, wherein the signal adjustment unit selects one of the adjustment units to adjust the first signal according to the voltage detection signal and the frequency detection signal. ### Claim 11 (depends on 8) The semiconductor memory module as claimed in claim 8, wherein the adjusting parameters are delay times. ### Claim 12 (depends on 8) The semiconductor memory module as claimed in claim 8, wherein the adjusting parameters are amplification ratios. ### Claim 13 (depends on 8) The semiconductor memory module as claimed in claim 8, wherein the voltage detector comprises: a voltage dividing unit coupled between the external power voltage and a ground voltage to generate a divided voltage; and a comparator comparing the divided voltage and an internal reference voltage to generate the voltage detection signal with different logic levels. ### Claim 14 (depends on 8) The semiconductor memory module as claimed in claim 8, wherein the semiconductor memory module is a semiconductor memory device. ### Claim 15 (depends on 8) The semiconductor memory module as claimed in claim 8, wherein the semiconductor memory module is a dynamic random access memory (DRAM). ### Claim 16 A signal adjustment method, comprising: detecting a voltage level of an external power voltage of a chip to generate a voltage detection signal; detecting frequency of a main clock of the chip to generate a frequency detection signal; obtaining a present operating region of the chip according to the voltage detection signal and the frequency detection signal; and selecting one of a plurality of adjusting parameters to adjust a first signal in the chip to generate a plurality of second signals and selectively output one of the second signals according to the obtained present operating region. ### Claim 17 (depends on 16) The signal adjustment method as claimed in claim 16, wherein the adjusting parameters are delay times. ### Claim 18 (depends on 16) The signal adjustment method as claimed in claim 16, wherein the adjusting parameters are amplification ratios.