Programmable logic controller and related electronic devices

A system including a programmable device including:

• at least one input interface and an input register for connection to the item under control to provide sampled and stored input data in digital form,
• at least one output interface and an output register for connection to the item under control to receive and store output data in digital form,
• programmable logic hardware including a plurality of basic logic elements and electrically configurable interconnections, said interconnections configurable to interconnect the logic elements as a user control program circuit and to connect the user control program circuit to said input and output interfaces,
• program loading circuits and/or software enabling the user to configure the programmable logic hardware with a user program circuit prior to commencing control, said user program circuit having a plurality of state data storage units storing the user program circuit state data,
• wherein said programmable device when configured contains a user program circuit interfaced to circuits and/or software, said circuits and/or software enabling the operating synchronously with the user program circuit , said circuits and/or software are able to communicate with a monitoring computer to respond to commands, said circuits and/or software are able to operate when commanded to cause the user program circuit to run, or pause, or single step, said circuits and/or software are able to read data values from said state data storage units and to write data values to said state data storage units, said circuits and/or software are able to pause the user program circuit in response to a signal originating in the user program circuit effective before the next active clock transition after that giving rise to the signal,
• said circuits and/or software being configured into the programmable logic hardware together with the user program circuit, and wherein said programmable device has an operating cycle of at least two non-overlapping sequential intervals, each interval consisting of one or more clock periods and during which,
• within a first said interval (the logic processing interval) an input data register operates to sample and store input data, and also the user program circuit operates to update its state data and allow the resultant combinational logic values to settle, and also an output data register operates to latch and store the output data, and
• within a second said interval (the data access interval) said circuits and/or software are enabled to read and write the user program circuit state data and cause control functions to be performed, and
• said programmable device includes circuits for selecting the programmable logic hardware clock frequency from a range of values, for the purpose of accommodating various user program circuit logic settling times;
• and
• a monitoring computer including:
• circuitss enabling the comparison of a known good reference set of user program circuit state data response patterns representing correct circuit operation with a test set of user program circuit state data response patterns, the test set representing actual circuit operation under the same circuit initial and stimulus conditions as the said reference set, but generated at a different selected clock frequency, such that differences in the patterns indicate incorrect circuit operation,
• circuits for repeating the tests and comparisons using different clock frequencies until the maximum allowable clock frequency at which the user program circuit will operate correctly has been found,
• said monitoring computer enabling the measurement of the maximum clock frequency at which the user program circuit will run without error.

A system including a programmable device including:

• at least one input interface and an input register for connection to the item under control to provide sampled and stored input data in digital form,
• at least one output interface and an output register for connection to the item under control to receive and store output data in digital form,
• programmable logic hardware including a plurality of basic logic elements and electrically configurable interconnections, said interconnections configurable to interconnect the logic elements as a user control program circuit and to connect the user control program circuit to said input and output interfaces,
• program loading circuits and/or software enabling the user to configure the programmable logic hardware with a user program circuit prior to commencing control, said user program circuit having a plurality of state data storage units storing the user program circuit state data,
• wherein said programmable device when configured contains a user program circuit interfaced to circuits and/or software, said circuits and/or software operating synchronously with the user program circuit , said circuits and/or software enabling the communication with a monitoring computer to respond to commands, said circuits and/or software enabling the operatation when commanded to cause the user program circuit to run, or pause, or single step, said circuits and/or software enabling the reading of data values from said state data storage units and to write data values to said state data storage units, said circuits and/or software enabling the pausing of the user program circuit in response to a signal originating in the user program circuit effective before the next active clock transition after that giving rise to the signal,
• said circuits and/or software enabling the configuration into the programmable logic hardware together with the user program circuit, and wherein said programmable device has an operating cycle of at least two non-overlapping sequential intervals, each interval consisting of one or more clock periods and during which,
• within a first said interval (the logic processing interval) an input data register operates to sample and store input data, and also the user program circuit operates to update its state data and allow the resultant combinational logic values to settle, and also an output data register operates to latch and store the output data, and
• within a second said interval (the data access interval) said circuits and/or software are enabled to read and write the user program circuit state data and cause control functions to be performed, and
• circuits and/or software enabling the detecting of transitions on selected signals within the user program circuit including:
• circuits and/or software enabling selectively performing, for each selected signal, at least one of:
• enabling or disabling the detection of transitions on the signal,
• reading the existing level of the signal,
• selecting the polarity of the transition to be detected, positive going, negative going or both, that will generate a trigger, and
• detecting whether a trigger condition has occurred during the last operational clock cycle;
• and
• circuits and/or software enabling the settings of the for detecting transitions, for each selected signal, to be changed by the monitoring computer during a data access interval while the user program circuit continues to operate multi-tasked;
• and
• a monitoring computer including:
• circuits and/or software enabling the displaying of one or more user program circuit selected signal waveforms without polling a shift chain, for each waveform said circuits and/or software enabling the displaying being driven by transitions occurring on the signal, said waveform being defined by the initial waveform level and the cycle counts at which the transitions occur.

A system including a programmable device including:

• at least one input interface and an input register for connection to the item under control to provide sampled and stored input data in digital form,
• at least one output interface and an output register for connection to the item under control to receive and store output data in digital form,
• programmable logic hardware including a plurality of basic logic elements and electrically configurable interconnections, said interconnections configurable to interconnect the logic elements as a user control program circuit and to connect the user control program circuit to said input and output interfaces,
• program loading means enabling the user to configure the programmable logic hardware with a user program circuit prior to commencing control, said user program circuit having a plurality of state data storage units storing the user program circuit state data,
• wherein said programmable device when configured contains a user program circuit interfaced to circuits and/or software , said circuits and/or software enabling operating synchronously with the user program circuit, said circuits and/or software enabling the o communication with a monitoring computer to respond to commands, said circuits and/or software enabling operation when commanded to cause the user program circuit to run, or pause, or single step, said circuits and/or software enabling the reading of data values from said state data storage units and to write data values to said state data storage units, said circuits and/or software enabling the pausing of the user program circuit in response to a signal originating in the user program circuit effective before the next active clock transition after that giving rise to the signal,
• said circuits and/or software enabling the configuration into the programmable logic hardware together with the user program circuit, and wherein said programmable device has an operating cycle of at least two non-overlapping sequential intervals, each interval consisting of one or more clock periods and during which,
• within a first said interval (the logic processing interval) an input data register operates to sample and store input data, and also the user program circuit operates to update its state data and allow the resultant combinational logic values to settle, and also an output data register operates to latch and store the output data, and
• within a second said interval (the data access interval) said means of control is enabled to read and write the user program circuit state data and cause control functions to be performed;
• and
• a monitoring computer enabling the display of user program circuit signal waveforms and optionally other data, the monitoring computer including:
• circuits and/or software enabling the reading of the user program circuit state data representing the signals and data to be displayed,
• circuits and/or software enabling the single stepping of the user program circuit, and
• circuits and/or software enabling therepeating of said reading and single stepping for the required number of clock cycles.